VLSI Mentoring

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Learn from those who've been there

Real interview experiences, success stories, and open discussion across every hardware & VLSI domain — shared by candidates and engineers.

Real interview loops shared by the community — rounds, outcomes, and what actually got asked.

NVIDIA

Design Verification Engineer · New grad

Offer
Design Verification
Hard

Very testbench-architecture heavy. They wanted to see me reason about coverage closure and reuse, not just recite UVM boilerplate.

Rounds

  1. 1Recruiter screen — Resume, projects, availability
  2. 2Technical phone — SystemVerilog, UVM phases, a coverage puzzle
  3. 3Onsite 1 — Build a testbench for a FIFO from scratch
  4. 4Onsite 2 — Assertions (SVA), debugging a failing sim
  5. 5Onsite 3 — Behavioral + team fit

Tips

  • Be able to write a driver/monitor/scoreboard on a whiteboard cold.
  • Have one project where you closed coverage and can talk numbers.
  • Practice explaining |-> vs |=> and clocking blocks precisely.

— anon_dv

AMD

Physical Design Engineer · Senior

Offer
Physical Design
Hard

Deep on real signoff scenarios: 'your block fails hold at the SS corner after CTS, walk me through what you do.' They probe for hands-on tapeout experience.

Rounds

  1. 1Recruiter screen — Node experience, tools (Innovus/ICC2)
  2. 2Technical 1 — Floorplanning, power planning, congestion
  3. 3Technical 2 — Timing closure across corners, ECOs
  4. 4Manager round — Ownership stories, cross-team work

Tips

  • Know your flow end to end and where you personally made decisions.
  • Bring specifics: utilization %, wns/tns numbers, how you fixed them.
  • Be ready for congestion vs timing trade-off discussions.

— pd_staff

Intel

STA Engineer · New grad

Rejected
Static Timing Analysis
Medium

I nailed the fundamentals but stumbled on a multi-clock CDC timing question. Fair process, quick feedback.

Rounds

  1. 1Phone screen — Setup/hold basics, SDC constraints
  2. 2Onsite 1 — Multicycle & false paths, CDC
  3. 3Onsite 2 — A tricky hold-violation root-cause question

Tips

  • Draw the timing path — don't answer setup/hold from memory alone.
  • Understand why hold fails are fixed with delay, not clock period.
  • Review CDC synchronizers and metastability MTBF intuition.

— newgrad_sta

Qualcomm

DFT Engineer · Mid

Offer
Design for Test
Medium

Focused and practical. They cared about coverage-vs-pattern-count trade-offs and how I debug test escapes.

Rounds

  1. 1Recruiter screen — Scan/ATPG background
  2. 2Technical 1 — Scan insertion, compression ratios
  3. 3Technical 2 — Debugging a low-coverage pattern set

Tips

  • Explain scan compression and its limits clearly.
  • Have a story about improving coverage or reducing pattern count.
  • Know BIST vs ATPG use cases.

— dft_mid

Arm

RTL Design Engineer · New grad

Offer
RTL Design
Hard

Lots of live RTL. They want clean, synthesizable code and clear reasoning about timing vs area.

Rounds

  1. 1Phone screen — FSM design, blocking vs non-blocking
  2. 2Onsite 1 — Design a round-robin arbiter in SystemVerilog
  3. 3Onsite 2 — Pipelining and hazard handling
  4. 4Onsite 3 — Behavioral

Tips

  • Practice writing arbiters, FIFOs, and CDC-safe RTL on a whiteboard.
  • Always state your assumptions and reset strategy.
  • Explain your always_ff vs always_comb choices.

— rtl_ng

Apple

Silicon Validation Engineer · Mid

Pending
Silicon & System Validation
Medium

Scenario-driven. They simulate a bring-up problem and watch how you structure debug and isolate root cause.

Rounds

  1. 1Recruiter screen — Post-silicon experience
  2. 2Technical 1 — Bring-up plan for a new SoC block
  3. 3Technical 2 — Lab debug: signal looks wrong, what next?

Tips

  • Have a structured debug methodology you can articulate.
  • Know your lab equipment and what each measurement tells you.
  • Correlate silicon behavior back to RTL/spec.

— val_mid