All roadmaps
RTL6 weeks24 tasksNew grad → mid-level
RTL / micro-architecture interview roadmap
Six weeks from synthesizable SystemVerilog and building blocks to clock-domain crossing, protocols and timing-aware design — the way RTL loops actually probe you.
By the end you'll be able to
- Write clean, synthesizable RTL for FIFOs, arbiters and pipelines
- Handle every clock-domain-crossing case with confidence
- Reason about area/timing/power trade-offs in interviews
This roadmap is coming soon
We're building the Design Verification track end to end first. Start there — RTL / Micro-architecture Design is next in line.