Interview Questions

Analog Devices

Precision analog & mixed-signal; deep AMS and validation loops.

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Interview process

  1. 1
    Recruiter screen

    Background and domain interest

  2. 2
    Technical phone screen

    Analog fundamentals

  3. 3
    Onsite: circuits deep-dive

    Op-amps, bandgaps, PLLs, data converters

  4. 4
    Onsite: system reasoning

    Spec-to-topology trade-offs and debug

  5. 5
    Hiring manager & behavioral

    STAR stories, project deep-dive, team fit and salary discussion

Free sample questions

3 free
Q1
Hard
Analog / RF

What is phase margin and why does a rule-of-thumb target ~60° matter?

Answer

Phase margin is 180° minus the loop's phase at the unity-gain frequency; it quantifies stability. Around 60° gives a good compromise: minimal peaking/overshoot and a fast, well-damped step response. Too little margin causes ringing or oscillation; too much makes the loop sluggish.

Compensation (e.g., Miller) is used to set phase margin — a common follow-up.

Q2
Easy
Analog / RF

A differential pair's ability to reject signals common to both inputs is quantified by:

  • PSRR
  • CMRR
  • THD
  • SNR

CMRR (common-mode rejection ratio) measures how well the amplifier rejects common-mode signals relative to differential gain — key for noise immunity.

Q3
Medium
Analog / RF

What is the gain-bandwidth product (GBW) of an op-amp?

Answer

For a dominant-pole amplifier, GBW is roughly constant: the open-loop DC gain times the dominant-pole frequency equals the unity-gain frequency. Raising closed-loop gain lowers available bandwidth proportionally.

GBW lets you estimate the bandwidth you'll get at a chosen closed-loop gain — a core analog design trade.

Full question bank

7 locked
What is the difference between pre-silicon and post-silicon validation?
Medium
What does a shmoo plot show?
Medium
Why are decoupling capacitors placed close to a chip's power pins?
Medium
What is crosstalk, and name one way to reduce it.
Medium
An unterminated fast transmission line most directly causes:
Medium
Which ADC architecture is best known for very high speed at moderate resolution?
Medium
Name the basic building blocks of a charge-pump PLL.
Hard

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Mentors who work at Analog Devices

KW
Kenji Watanabe
Staff Analog/Mixed-Signal Engineer
4.7
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