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RTL/DV fundamentals
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Free sample questions
3 freeQ1
Easy
DV
In a testbench, why do you sample DUT outputs on the opposite clock edge (or after a small skew) from the one that drives inputs?
Answer
Driving on one edge and sampling on the other avoids racing the clock edge where the DUT updates. It gives combinational outputs time to settle and prevents the testbench from reading old or metastable values, matching how real synchronous logic is observed.
This is the practical reason clocking blocks in SystemVerilog have input/output skews — they formalize where in the cycle the TB samples and drives.
Q2
Medium
DV
Explain the difference between `rand` and `randc` in SystemVerilog.
Answer
`rand` is standard random — each randomize() call picks a value independently, so repeats are possible. `randc` is random-cyclic — it walks through every value in the domain once (in random order) before any value repeats.
randc is handy for cycling through opcodes or addresses to guarantee coverage, but on wide fields it is costly, so it is usually reserved for small enumerated domains.
Q3
Medium
DV
Name the standard UVM phases in order and say which one is time-consuming.
Answer
build_phase (top-down) → connect_phase (bottom-up) → end_of_elaboration → start_of_simulation → run_phase (the only time-consuming phase, runs in simulation time) → extract → check → report → final. The run_phase also has 12 sub-phases (reset, configure, main, shutdown, etc.).
Knowing build is top-down (parents build children first) and connect is bottom-up is a frequent follow-up.
Full question bank
1065 lockedIn a UVM agent, which component drives transactions onto the DUT interface?
Easy
What is the role of a scoreboard in a UVM testbench?
Easy
The stuck-at fault model assumes a faulty node is:
Easy
How does dynamic switching power scale with supply voltage V?
Easy
What does clock tree synthesis (CTS) accomplish?
Easy
In a timing report, what does negative slack indicate?
Easy
A clock divide-by-2 is most simply built from:
Easy
Which statement about Verilog `wire` vs `reg` is correct?
Easy
Difference between byte a and bit [7:0] a.
Easy
What is the difference between bit and logic?
Easy
Why logic is introduced in SV? Or Why reg and wires are not sufficient?
Easy
Difference between reg and logic?
Easy
What are 2 state and 4 state variables? Provide some examples.
Easy
Difference between integer and int
Easy
Difference between packed and unpacked arrays
Easy
Difference between dynamic and associative arrays
Easy
Difference between dynamic array and queue
Easy
Difference between structure and union
Easy
How do you write a power b in sv code?
Easy
What are pass-by-value and pass-by-reference methods?
Easy
Why do we need randomization in SystemVerilog?
Easy
Difference between module and program block?
Easy
How do program block avoid the race condition?
Easy
Difference between === and == operators?
Easy
What are SystemVerilog interfaces and why are they introduced?
Easy
What is modport and clocking block?
Easy
Difference between initial and final block.
Easy
What is cross-coverage?
Easy
Difference between code and functional coverage
Easy
Write rand constraint on a 3 bit variable with distribution 60% for 0 to 5 and 40% for 6,7. Write coverpoint for the same.
Easy
How many types of arrays are there? Explain
Easy
Why do we need UVM methodology?
Easy
Difference between uvm_object and uvm_component
Easy
Difference between uvm_transaction and uvm_sequence_item
Easy
Difference between create and new() The new method is a constructor for SystemVerilog classes to create an object instance.
Easy
Difference between copy and clone.
Easy
Difference between uvm_resource_db and uvm_config_db
Easy
What is severity and verbosity in UVM?
Easy
Difference between sequence and sequencer.
Easy
How to run any test case in UVM?
Easy
Write a simple uvm sequence template and explain each line.
Easy
How is scoreboard connected to different components?
Easy
Difference between blocking and non-blocking assignments
Easy
Difference between task and function
Easy
Difference between wire and reg
Easy
What is generate block in Verilog and its usage?
Easy
Difference between while and do-while loop
Easy
What is an automatic keyword in the task?
Easy
Explain the difference between a static and automatic function with example.
Easy
Difference between $stop and $finish.
Easy
Difference between $random and $urandom
Easy
What is AHB and why is it used?
Easy
Where is AHB normally used in an SoC?
Easy
What is the difference between AHB and APB?
Easy
What are the address phase and data phase in AHB?
Easy
How do you identify a valid AHB transfer?
Easy
What are the possible values of HTRANS?
Easy
What is APB and why is it used?
Easy
Which peripherals are commonly connected to APB?
Easy
Why is APB considered low power and simple to use?
Easy
What are the phases of an APB transfer?
Easy
When exactly does an APB transfer complete?
Easy
What is the difference between PSEL and PENABLE?
Easy
What is AXI and why is it used?
Easy
What is the difference between AXI and AHB?
Easy
What are the five AXI channels?
Easy
What is the VALID/READY handshake in AXI?
Easy
Explain an AXI write transaction.
Easy
Explain an AXI read transaction.
Easy
Different types of code coverage.
Easy
Difference between create and new()
Easy
Explain the difference between blocking (=) and non-blocking (<=) assignments in Verilog, and state which to use for sequential vs combinational logic.
Medium
What common coding mistake infers an unintended latch during synthesis of combinational logic?
Medium
One-hot FSM state encoding versus binary encoding primarily trades:
Medium
Why is a two-flop synchronizer used for a single-bit clock-domain-crossing signal?
Medium
What is the difference between code coverage and functional coverage?
Medium
In SystemVerilog Assertions, what does `a |=> b` mean?
Medium
What is a scan chain and why is it inserted?
Medium
Define controllability and observability in the context of testability.
Medium
What is the difference between clock gating and power gating?
Medium
Multi-Vt cell libraries let a designer:
Medium
What is the antenna effect, and name one fix.
Medium
High placement congestion most directly harms:
Medium
Define setup time and hold time, and describe what a hold violation implies about a path.
Medium
A hold-time violation is correctly fixed by:
Medium
Contrast $display, $write, $monitor, and $strobe in Verilog.
Medium
Why is a virtual interface needed in a class-based SystemVerilog testbench?
Medium
In SystemVerilog, `fork ... join_none` behaves how relative to the following statement?
Medium
What problem do UVM objections solve, and what is the modern alternative?
Medium
What is the correct driver–sequencer handshake in UVM?
Medium
What is the uvm_config_db used for, and what is a common pitfall?
Medium
What does `disable iff` do in a concurrent SVA property, and why is it important?
Medium
In SVA, `req |-> ##[1:3] gnt` requires that:
Medium
What is cross coverage, and why can it explode the number of bins? How do you keep it manageable?
Medium
Differentiate illegal_bins from ignore_bins in a covergroup.
Medium
What goes into a verification plan, and how does coverage tie back to it?
Medium
Name the five AXI channels and explain why read and write use separate channels.
Medium
In an AXI VALID/READY handshake, a transfer occurs on the clock edge where:
Medium
You have 500 regression logs. Describe a scripting approach to summarize pass/fail and extract the first error from each failure.
Medium
What is DPI-C in SystemVerilog and when would you use it?
Medium
A constrained-random test fails only with certain seeds. Walk through how you debug it.
Medium
How do you size an asynchronous FIFO between a fast producer and a slow consumer for a burst of N writes?
Medium
Why must a multi-bit bus crossing clock domains use gray coding or a handshake instead of per-bit synchronizers?
Medium
Compare fixed-priority and round-robin arbiters. When would you pick each?
Medium
Why is a dedicated integrated clock-gating (ICG) cell used instead of an AND gate on the clock?
Medium
What does test compression (e.g., EDT) buy you, and what is the trade-off?
Medium
Which fault model targets timing-related (slow-to-switch) defects?
Medium
Write an assertion to check clock period of 100 MHz.
Medium
Write an assertion to check clock frequency and duty cycle with +/- 5% error.
Medium
Write a constraint to generate unique values in rows for a multidimensional array.
Medium
Write a constraint to generate diagonal values should be same in a multidimensional array.
Medium
Write a constraint to generate an address where 9 bits are always set to 1, and sequences of 111 or 000 should not occur in a 16-bit address.
Medium
Write a Constraint to generate a pattern 5,-10,15,-20,25.....
Medium
Write a constraint to generate an address for different ports like port_0, port_1, port_2 and each Port is having starting and ending Address.
Medium
Write a constraint to generate a pattern 9,99,999,9999,99999,..
Medium
Write a constraint to generate the Fibonacci series.
Medium
Write a constraint to generate palindrome.
Medium
Write a constraint to generate Prime numbers in different ways.
Medium
Write a constraint to randomly generate 10 unique prime numbers in an array between 1 and 200 & generated prime numbers should have 7 in unit Place (eg :7,17,37....)
Medium
Write a constraint to implement randc construct using rand keyword.
Medium
Write a constraint to generate a pattern of 0011223344...
Medium
Write a constraint to generate a pattern of 000111222333444555...
Medium
Write an SV constraint to make diagonal elements Zero.
Medium
What is wrong with the below code? What is the correct process to write the constraint?
Medium
Write a single constraint to generate random values for bit [8:0] variable in the below range, 1-34, 127, 129-156, 192-202,257-260.
Medium
Write a constraint without an inside function to generate random values within the range of 34 to 43?
Medium
Write a constraint to generate a random value for a var1 [7:0] within 50 and var2 [7:0] with the non-repeated value in every randomization?
Medium
Write a constraint to generate 0, 1, x and z randomly.
Medium
Write a constraint to generate multiples of power 2.
Medium
Write a constraint with array size 5 to 10 values & the array values should be in ascending order/descending order.
Medium
Write a constraint to generate a pattern 0102030405.
Medium
Write a constraint - divisible by 5.
Medium
Derive odd numbers within the range of 10 to 30 using SV constraint.
Medium
Write a constraint to generate prime numbers between the range of 1 to 100.
Medium
What is circular dependency and how to avoid this problem?
Medium
How can we generate the factorial of the first 5 even numbers using constraints in SystemVerilog?
Medium
How can you generate a random number within a specified range using SystemVerilog?
Medium
What is the constraint to generate the pattern 9 7 5 3 1 8 6 4 2 0 ?
Medium
Write a constraint sunch that array size between 5 to 10 values of the array are in asscending order ?
Medium
Can you provide a code example of how to use constraints to access a single bit of a 16-bit variable?
Medium
Write a constraint to generate a variable with 0-31 bits should be 1, 32-61 bits should be 0.
Medium
How to generate a sequence of 10 random single-bit values that alternate between 0 and 1 like 101010101010?
Medium
Write a SystemVerilog program to randomize a 32-bit variable, but only randomize the 12th bit.
Medium
How can you define a constraint in SystemVerilog to ensure that even locations in a random array contain odd numbers, and odd locations contain even numbers?
Medium
Define: (a) bit (b) nibble (c) byte (d) word
Medium
What is weighted code? Give example.
Medium
Give an example for Non-weighted code?
Medium
What is the key feature of Excess-3 code?
Medium
In how many different ways can number 5 be represented using 2-4-2-1 code?
Medium
What are all the BCD numbers that can be uniquely represented in 2-4-2-1 weighted code?
Medium
How many unused combinations are there in the representation of BCD numbers using 7-4-2-1 weighted scheme? What are they?
Medium
What is the condition for a weighted code to be self-complementary?
Medium
Convert the Gray code number 11001 to binary code?
Medium
Give the procedure for converting a binary number to Gray code?
Medium
Represent 45 in the number systems (a) binary (b) BCD (c) Excess-3 (d) Gray code
Medium
What will be the result if all the zeros are retained from LSB side until 1 is seen, including that 1, and complement all the following bits of a binary number?
Medium
In a particular design which uses 5 bits for integral part and 7 bits for fractional part,the result of some operation is 7B8 hex. Find the corresponding decimal equivalent?
Medium
Explain the detailed procedure for BCD addition?
Medium
Which gates are called universal gates? Why?
Medium
How many minterms or maxterms will be there for n-inputs?
Medium
In how many ways can a NAND gate be converted into an inverter? Show all the possibilities?
Medium
How many number of 2 input AND gates are required to generate N I/P AND gate?
Medium
(a) If it is given that A & B will not be 1 at the same time, what will be the equivalent logical gate for an XOR gate? (b) If any of the inputs of an XOR gate are inverted, XOR gate will work as ----- ?
Medium
State the Shannon’s expansion theorem for representing a Boolean function by its co-factors?
Medium
Mention the logical gates for which the 3 input implementation can not be obtained from two 2 input gates? How do you implement them?
Medium
Give implementation of XOR using minimum number of NAND gates?
Medium
Majority function is the one which gives 1 if the input has more 1s than 0s. Show the truth table and give the AOI for 3-input majority function?
Medium
Explain parity generation and its significance?
Medium
Which logical gates can be used as parity generators?
Medium
What is the parity of (i) 10111001 (ii) 11001010
Medium
Give a circuit for 4-bit even parity checker? And explain the same how can it be reused for parity generation?
Medium
Design a combinational circuit using XOR gates that converts a 4-bit gray code number to a 4-bit binary number?
Medium
Which logical gate can be used to find out whether the two single bit inputs are equal or not?
Medium
How to obtain the dual of a Boolean equation?
Medium
Define: SOP from and POS form?
Medium
When is a SOP/POS form is called standard or canonical?
Medium
Why do we write 00 01 11 10 in that order while Drawing K-maps?
Medium
What do you mean by don’t care condition?
Medium
Y = A'C + AC'B' and you are given that A=C=1 will never occur. Simplify Y?
Medium
Generalization of Q13: The grouping of k adjacent cells, in a N variable K-Map will lead to a term of ----- literals?
Medium
In the simplification of a Boolean function, F = ∑ (0,1,2,6,7,8,9,10,14,15) using QM method the following table is obtained: Q1) Define: SOP from and POS form?
Medium
Simplify the Boolean function Y = ∑ ( 0,2,3,5,7,10,11,15) in POS form using KMap?
Medium
Give the AND-OR implementation of a circuit, using minimum gates, that gives HIGH when the input is BCD equivalent of 5,7 or 9 and LOW otherwise. ?
Medium
(a) Show the AOI implementation of a 2:1 Mux? (b) Convert this to 2-input NAND implementation?
Medium
Design the following gates using minimum number of 2:1 Muxes? (a) NOT (b) AND (c) OR (d) XOR
Medium
Design a circuit for 3-input majority function using a 4:1 Mux?
Medium
(a) Expand the Boolean function f(x,y,z) = x’z’ + xy + xz in terms of x? (b) Implement f using a 2:1 Mux and external gates?
Medium
There is a single telephone which needs to transmit the data from 8 different users to the receiving end. Give a design which can accomplish this task?
Medium
You are given a 2:4 decoder, a 2 input OR gate and a 3 input OR gate. Using these components design a system which takes A & B as inputs and generates the following four outputs: AB, (AB)' , A+B, (A+B)'.
Medium
Design a circuit for half-subtractor using basic gates?
Medium
Design "OR" gate using HA's?
Medium
Design a full adder using half-adders and minimum number of external gates?
Medium
Implement a full adder using two 4:1 Muxes?
Medium
A full adder can be implemented using basic gates in many ways. Show the efficient implementation among them, which needs minimal hardware?
Medium
Implement a circuit for adding two 4-bit numbers using (a) Ripple carry adder (b) Carry Look Ahead (CLA) adder
Medium
Compare the two implementations of Q15.
Medium
If each XOR gate has a propagation delay of 10ns and AND/OR gate has a delay of 5ns each (irrespective of number of inputs), what is the total propagation delay in adding two 4 bit numbers in case of (a) Normal full adder (b) Carry Look Ahead adder.
Medium
Explain how a full adder can be used as majority function?
Medium
Give the truth table of full subtractor? Design the same using full adder?
Medium
There is a sixteen bit adder with ripple carry. Which of the following gives minimum delay for the output? (Fastest output) F0 + F1, FF + FF, FF + F1
Medium
What is overflow? Under what conditions will it occur?
Medium
Using a 4-bit binary adder, design a circuit which multiplies the input by 3?
Medium
Design a subtractor unit using a 4-bit comparator, 4-bit binary adder and some external gates, which performs A-B if A>B and else B-A. A and B are two 4-bit binary numbers.
Medium
Design an adder/subtractor unit using 4-bit binary adder and some external gates, which gives out A+B if C=0 and A-B if C=1. Also provide an indicator for checking the overflow?
Medium
Use the above designed circuit as block box and give a scheme for finding the absolute value of a 4-bit number?
Medium
Design a circuit that generates 9’s compliment of a BCD digit using binary adder?
Medium
Give the circuit that adds two BCD numbers and gives out a BCD number?
Medium
How will you count the number of 1's that are present in a given 3-bit input using full adder?
Medium
Give the truth table for 4:2 priority encoder in which the LSB(D0) has the highest priority and MSB(D3) has the lowest priority.
Medium
You have three delay elements D1, D2, D3 that delay a clock by 25%,50% and 75% respectively. Design a frequency doubling (fout = 2 * fin) circuit that uses these delay elements along with any combinational logic.
Medium
Give a combinational circuit which checks out whether two 4-bit input signals are same or not?
Medium
Using a 4:16 decoder and minimum number of external gates implement the following Boolean functions: (a) F(A,B,C,D) = ∑ (5,7,9,14) (b) G(A,B,C,D) = ∑ (0,1,2,3,4,6,7,8,9,10,11,14,15)
Medium
Mention two basic applications of flip-flops?
Medium
What is the difference between a LATCH and a Flip flop?
Medium
What is transparent latch?
Medium
Implement S-R Latch with control input using 2-input NAND gates?
Medium
Design a master-slave D-Flip flop using D-Latch?
Medium
What is race-around condition? Explain it in case of J-K Latch and solution to avoid that?
Medium
We have a circular wheel with half painted black and the other half painted white. There are 2 censors mounted 45 degree apart at the surface of this wheel( not touching the wheel) which give a "1" for black and "0" for white passing under them. Design a circuit, using DFF to detect which way the wheel is moving. Can not assume any fixed position for start.
Medium
Give the characteristic table and characteristic equation for J-K Flip-flop?
Medium
Construct a J-K flip flop using a DFF, 2:1 Mux and an-inverter?
Medium
What is excitation table?
Medium
Write the excitation table for T-flip flop?
Medium
Draw the circuit for a D flip flop with Synchronous Reset?
Medium
Which flip-flop can be used as delay switch?
Medium
Which flip-flop can be used as toggle switch?
Medium
Using DFFs and minimum no. of 2×1 Mux, implement the following XYZ flip-flop.
Medium
Show how the AB flip-flop can be converted to a D flip-flop?
Medium
In C-N (Change-No change) flip flop, there won’t be any change in output as long as N is 0, irrespective of C. If N=1, then if C = 0 output will change to zero else if C =1 output will be the compliment of previous output. (a) Write the characteristic table ? (b) Design this using J-K flip-flop?
Medium
Give the State Machine for Serial 2’s complementer. Draw the complete design for the same using DFF?
Medium
Give the state transition diagram for J-K flip flop?
Medium
What is Moore model & Mealy model? Explain.
Medium
Give the State Machine for detecting the sequence “1010” from a serially coming data.
Medium
Repeat Q7 for Non-overlapping case.
Medium
Draw the state diagram to output a "1" for one cycle if the sequence "0110" shows up and the leading 0s cannot be used in more than one sequence.
Medium
Describe a finite state machine that will detect three consecutive coin-tosses (of one coin) that result in heads.
Medium
Reduce the following state table:
Medium
Starting from state a, write the next state and output values for the input sequence: 01010101001 for both Original and reduced state table.
Medium
What is one-hot method? List the advantages and disadvantages?
Medium
How many flip flops are needed to design a FSM having N states if the state assignment is done by using (a) Binary (b) Gray (c) One hot (d) Johnson
Medium
For the above problem, which method is more suitable for state assignment?
Medium
Draw the state diagram for a circuit that outputs a "1" if the aggregate serial binary input is divisible by 5. For instance, if the input stream is 1, 0, 1, we output a "1" (since 101 is 5). If we then get a "0", the aggregate total is 10, so we output another "1" (and so on).
Medium
Draw the FSM for checking whether the two inputs P and Q have same value for the last three continuous samples?
Medium
If the number of 1s in inputs X and Y since reset is multiple of 4, the output is 1 and 0 otherwise. Give the FSM required for designing of the sequential circuit?
Medium
Define (a) setup time (b) hold time (c) clock to Q delay.
Medium
Which of the following flip flops can work at maximum frequency?
Medium
For the above configuration with dly = 0, which of the flip flops that are shown in Q2, can be used if the available clock period is (a) 5ns (b) 8ns (c) 15ns
Medium
Design a circuit for clock frequency divided by 2 using DFF. Given the following information, find the maximum clock frequency that the circuit can handle? T_setup = 6ns , T_hold = 2ns and T_propagation = 10ns
Medium
Is there any hold violation in the above circuit? When will the hold violation occur in a given circuit and how can it be solved in circuit level? Describe in detail.
Medium
What is clock skew? Explain.
Medium
Can hold time be negative? Explain.
Medium
The following digital circuit shows two flops with a logic delay (dly1) in between and two clock buffer delays (dly2, dly3). Derive the conditions in terms of (dly1,dly2,dly3) to fix setup and hold timing violations at the input of second FF? Tcq – Clock to Q delay, Tsu -- Setup time and Th – hold time.
Medium
What is the maximum frequency of operation for the following configuration? .
Medium
What is metastability? When/why it will occur? Explain how to avoid this? .
Medium
For the circuit in Q11, two identical flip flops with the following data were used: Tsu = 2ns, Th = -3ns and Tcq = 5ns. Which combination of dly1 and dly2 from the following table will give maximum frequency of operation without any violations? Given: dly3 = 0. .
Medium
Design a 3-bit shift register using 2:1 Mux and D Flip Flops which shifts right if the control input, C = 0 and shifts left if C = 1?
Medium
What is the difference between a ripple counter and a synchronous counter?
Medium
Design a 4-bit binary counter using TFFs?
Medium
Give the FSM for a 3-bit gray code counter?
Medium
Design a frequency divide-by-2 circuit using DFF and external gates which gives (a) 50% duty cycle (b) 25% duty cycle?
Medium
Design frequency divide-by-3 circuit using DFFs and external gates which gives a duty cycle of 1/3rd?
Medium
How do you change the above design to get (a) 66.67% duty cycle (b) 50% duty cycle?
Medium
Design the Digital Circuit which gives fout = (2/3) fin
Medium
Here is an interesting design question. There is a room which has two doors one to enter and another to leave. There is a sensor in the corridor at the entrance and also at the exit. There is a bulb in the room which should turn off when there is no one inside the room. So imagine a black box with the inputs as the outputs of sensors. What should the black box be?
Medium
What is ring counter? Implement a ring counter using shift register?
Medium
The following FSM shows the zero circulating ring counter. Predict the values of the missing states?
Medium
What are the unused states in a 3-bit Johnson counter?
Medium
How many unused states will be there in a Johnson’s counter with N flip-flops?
Medium
What is the output frequency of a 4-bit binary counter for an input clock of 160 MHz?
Medium
How fast can a 11 stage ripple counter be clocked, assuming worst case clock to Q delay of 40ns (of each stage) and extra gate delays of 60ns?
Medium
Design a counter using DFF that counts in the sequence: 0,4,2,7,0,4,2,7,0,4……?
Medium
Using external gates and 4-bit counter, design a circuit which gives ‘1’ if the number of clocks are multiples of 4.
Medium
What are the frequencies F1, F2, F3 and F4 after each stage if an input clock of 10MHz is applied?
Medium
How to swap the contents of two 8-bit registers without using a third register.
Medium
What are stuck-at problems? Explain the reason for their occurrence?
Medium
How many number of stuck at problems are possible for a 2 input AND Gate? Which of those faults are not testable?
Medium
Define : (a) Test Pattern/Test set (b) ATPG
Medium
Explain the procedure for detecting a specific fault in a given circuit?
Medium
Give the test patterns that are needed to verify all the stuck at problems of a (a) 2- Input NAND Gate (b) 3-input NAND Gate
Medium
What do you mean by “Path Sensitized Tests” in testing of logic circuits?
Medium
(a) Give the circuit for a 4-bit parity generator? (b) Derive the minimal test set that can detect all stuck-at-faults?
Medium
What is D-notation?
Medium
What are the two hazards that can be there in a combinational circuit?
Medium
Give the characteristics of Static-zero Hazard?
Medium
Show the equivalent circuit for Static-one Hazard?
Medium
How to avoid static hazards in a given circuit(single variable change hazards)?
Medium
Find a hazard-free minimum cost implementation of the function: F(A,B,C,D) = ∑ (0,4,11,13,15) + d(2,3,5,10)
Medium
Design 4-input XOR gate using 2 input XOR gates in all possible ways? Discuss the advantages and disadvantages of each?
Medium
What do you mean by CMOS technology? Explain with a block diagram.
Medium
What are the advantages and disadvantages of CMOS logic?
Medium
Show the circuit for CMOS inverter and explain the basic operation?
Medium
Draw the VTC of a CMOS inverter?
Medium
Arrange the following in the decreasing order of voltage levels: VOH,VOL,VIH,VIL.
Medium
Define: (a) Fan-out (b) Noise-margin
Medium
Find out fan_out and propagation delay of a logical gate for which the following specifications are given: VCC = 5V, ICCH = 1mA, ICCL = 2mA, IOH = 1mA, IOL = 20mA, IIH = 0.05mA and IIL = 2mA
Medium
Draw the CMOS implementation of NAND and NOR gates.
Medium
How many minimum number of MOS transistors are required to implement the Boolean function, Y (A,B,C) = AB + A’C + BC using CMOS implementation assuming the inputs and their complements are available?
Medium
How many minimum number of MOS transistors are required to implement a Full Adder using CMOS technology?
Medium
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
Medium
What do you mean by pass transistor logic?
Medium
Show the implementation of AND gate using pass transistor logic?
Medium
Show the circuit of Transmission gate and explain the functionality?
Medium
Why don’t we use just one NMOS or PMOS in a transmission gate?
Medium
Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output)
Medium
The output and input of a static CMOS inverter are connected as shown in the above figure. What is the output voltage?
Medium
What are the applications of open-collector gate?
Medium
What is Latch Up? How do you avoid Latch Up?
Medium
What is Volatile memory? Give an example.
Medium
Differentiate between RAM and ROM?
Medium
How many address and data lines will be there for a memory of size, 1K X 8?
Medium
How many number of 16X8 size memories are needed to obtain a memory of size 256X16?
Medium
Using DFF design a binary cell, which can perform read/write operations based on enable, r/w ? Also provide memory enable, mem_en?
Medium
Give the basic circuit for DRAM?
Medium
Draw the circuit for SRAM?
Medium
Define memory access time?
Medium
What are the advantages and disadvantages of DRAM when compared to SRAM?
Medium
Explain read-refresh operation in case of DRAM?
Medium
What is dual data ROM?
Medium
Expand the following: (a) PLD (b) PLA (c) PAL (d) FPGA
Medium
What is the difference between PLA and PAL?
Medium
What is FIFO? Explain the significance?
Medium
Show the basic block diagram of FIFO and explain the basic signals or connections of a FIFO?
Medium
It is required to connect a Master, which generates data @ 200 Mega Samples/sec to a Slave which can receive the data @ 10 Mega Samples/Sec. If the data lasts in 10Micro Sec, what is the optimal size of FIFO to be used to avoid loose of data?
Medium
In a particular system, the sender sends data at the rate of 80 words / 100 clocks and the receiver can consume at the rate of 8 words / 10 clocks. Calculate the depth of FIFO so that no data is dropped under following assumptions: - There is no feedback or handshake mechanism. - Occurrence of data in that time period is guaranteed but exact place in those clock cycles is indeterminate.
Medium
What is the difference between Synchronous and Asynchronous FIFOs?
Medium
Explain how to inject a CRC error in a packet which has just data and CRC fields.
Medium
How do you know when verification is completed?
Medium
How to avoid race condition between Testbench and DUT?
Medium
What is a semaphore?
Medium
What is the need of regression?
Medium
What is randomization?
Medium
What is the significance of seed in randomization?
Medium
What is the difference between code coverage and functional coverage?
Medium
If code coverage is 100% and functional coverage is not, what does it mean?
Medium
If functional coverage is 100% and code coverage is not, what does it mean?
Medium
What is the difference between a passive monitor and an active monitor?
Medium
Under what condition should simulation end in a simulation environment?
Medium
What is a scoreboard?
Medium
How are test cases included in the simulation environment?
Medium
What are the different ways test cases are included for simulations?
Medium
Write code for a clock generator.
Medium
What is a test plan? What it contains?
Medium
Explain some coding guidelines that you followed in your environment?
Medium
Explain about white/black box testing and gray-box testing.
Medium
In a packet protocol, where is the packet comparison done?
Medium
What are scalars in Perl? Provide an example demonstrating the usage of scalars.
Medium
Explain the concept of arrays in Perl. How are arrays used, and what are some common array operations?
Medium
What are hashes in Perl? How are hashes used, and what are some common hash operations?
Medium
Explain the concept of control structures in Perl. What are conditional statements and loops, and how are they used in Perl programming? Provide examples.
Medium
What are regular expressions in Perl? How are regular expressions used, and what are some common applications of regular expressions?
Medium
Explain the concept of subroutines in Perl. What are subroutines, and how are they used in Perl programming? Provide an example demonstrating the usage of subroutines.
Medium
What is the significance of the use strict and use warnings pragmas in Perl? How do they help in writing better Perl code?
Medium
Explain the concept of file handling in Perl. How can you open, read, write, and close files in Perl? Provide an example demonstrating file operations.
Medium
What are modules in Perl? How are modules used, and why are they beneficial in Perl programming?
Medium
Explain the concept of references in Perl. What are references, and how are they used in Perl programming? Provide an example demonstrating the usage of references.
Medium
Explain the concept of modules in Perl. What are modules, and how are they used in Perl programming? Provide an example demonstrating the usage of modules.
Medium
Explain the concept of object-oriented programming (OOP) in Perl. What is OOP, and how is it implemented in Perl? Provide an example demonstrating the usage of OOP in Perl.
Medium
Explain the concept of exceptions in Perl. What are exceptions, and how are they handled in Perl programming? Provide an example demonstrating the usage of exceptions.
Medium
Explain the concept of regular expressions in Perl. What are regular expressions, and how are they used in Perl programming? Provide an example demonstrating the usage of regular expressions.
Medium
What is the purpose of the use strict and use warnings pragmas in Perl? How do they help in writing better Perl code? Provide an example demonstrating the usage of these pragmas.
Medium
Explain the concept of subroutine references in Perl. What are subroutine references, and how are they used in Perl programming? Provide an example demonstrating the usage of subroutine references.
Medium
What are anonymous subroutines in Perl? How are they different from named subroutines? Provide an example demonstrating the usage of anonymous subroutines.
Medium
Explain the concept of object serialization in Perl. What is serialization, and how is it used in Perl programming? Provide an example demonstrating the serialization and deserialization of an object in Perl.
Medium
Explain the concept of closures in Perl. What are closures, and how are they used in Perl programming? Provide an example demonstrating the usage of closures.
Medium
Explain the concept of tie in Perl. What is tying, and how is it used in Perl programming? Provide an example demonstrating the usage of tie.
Medium
Explain the concept of attributes in Perl. What are attributes, and how are they used in Perl programming? Provide an example demonstrating the usage of attributes.
Medium
Explain the concept of autovivification in Perl. What is autovivification, and how does it occur in Perl programming? Provide an example demonstrating autovivification.
Medium
Explain the concept of function signatures in Perl. What are function signatures, and how are they used in Perl programming? Provide an example demonstrating the usage of function signatures.
Medium
Explain the concept of the @INC array in Perl. What is @INC, and how is it used in Perl programming? Provide an example demonstrating the usage of @INC.
Medium
Explain the concept of source filters in Perl. What are source filters, and how are they used in Perl programming? Provide an example demonstrating the usage of source filters.
Medium
Explain the concept of multithreading in Perl. What is multithreading, and how is it used in Perl programming? Provide an example demonstrating the usage of multithreading.
Medium
Explain the concept of XS in Perl. What is XS, and how is it used in Perl programming? Provide an example demonstrating the usage of XS.
Medium
Explain the concept of memoization in Perl. What is memoization, and how is it used in Perl programming? Provide an example demonstrating the usage of memoization.
Medium
Write an assertion check to make sure that a signal is high for a minimum of 2 cycles and a maximum of 6 cycles.
Medium
Write an assertion for glitch detection.
Medium
Are following assertions equivalent:
Medium
Write an assertion: everytime when the valid signal goes high, the count is incremented.
Medium
When there's a no_space_err, the no_space_ctr_incr signal is flagged for exactly once clock.
Medium
Write an assertion checker to make sure that an output signal never goes X?
Medium
Write an assertion to make sure that a 5-bit grant signal only has one bit set at any time?
Medium
Write an assertion which checks that once a valid request is asserted by the master, the arbiter provides a grant within 2 to 5 clock cycles.
Medium
How can you disable an assertion during active reset time?
Medium
How can all assertion be turned off during simulation (with active assertions)?
Medium
Write an assertion: A high for 5 cycles and B high after 4 continuous highs of A and finally both A and B are high?
Medium
Write an assertion to verify the clock with 50% duty cycle of any given time period.
Medium
When signal "d" changes to 1, on next cycle, if signal "b" is true, then signal "c" should be
Medium
Write an assertion to check divide by 2 circuit output.
Medium
When signal_a is asserted, signal_b must be asserted, and must remain up until one of the signals signal_c or signal_d is asserted.
Medium
When the positive edge of signal "a" is detected, check signal "b" has to be high continuously until signal "c" goes low.
Medium
Whenever valid signal goes high enable signal should be asserted in the next cycle & it
Medium
Whenever the signal A goes high from the next cycle the signal B should repeat n no. of times, where n is equal to value of bit[3:0]C when signal A is asserted.
Medium
Write a Verilog to generate the three times multiplication table.
Medium
Write a Verilog code to implement a counter that cycles through two distinct ranges based on a mode: initially counting from 5 to 12, and then, upon reaching the end of this range, switching to count from 0 to 15.
Medium
Write a Verilog module that determines if a given number is even or odd, and outputs a result of 1 for even numbers and 0 for odd numbers using function.
Medium
Write a SystemVerilog code to identify and display numbers divisible by 8 within the range of 0 to 100?
Medium
Write a SystemVerilog program that utilizes a function to calculate the sum of two numbers and determine whether the result is odd or even.
Medium
How can you define a constraint in SystemVerilog to generate a 10-bit number where more than one bit is set to 1, but no two set bits are adjacent to each other?
Medium
Write the constraint to gen. this seq. 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 2 0 3 0 4 0 5 ... in array.
Medium
Write a constraint for an array of numbers such that the size of array ranges from 6 to 15
Medium
How to find indexes associated with associative array items?
Medium
Difference between fork-join, fork-join_any, and fork-join_none
Medium
Difference Between always_comb and always@(*)?
Medium
Difference between structure and class
Medium
Difference between static and automatic functions
Medium
Difference between new[ ] and new() new[ ] – To create a memory. It can also be used to resize or copy a dynamic array.
Medium
Difference between shallow and deep copy
Medium
How does the OOP concept add benefit in Verification?
Medium
What is inheritance?
Medium
What are the ‘super’ and ‘this’ keywords in SystemVerilog?
Medium
What is polymorphism and its advantages?
Medium
What is a virtual function?
Medium
What is the use of a scope resolution operator?
Medium
Difference between virtual and pure virtual function
Medium
What is a virtual interface and its need?
Medium
What is a virtual class?
Medium
What are parameterized classes?
Medium
What are rand and randc methods?
Medium
What are pre_randomize and post_randomize methods?
Medium
Explain bidirectional constraints
Medium
Is it possible to override existing constraints?
Medium
Difference between :/ and := operators in randomization Both are used to assign weightage to different values in the distribution constraints.
Medium
What is std::randomize?
Medium
Is it possible to call a function from constraint? If yes, explain with
Medium
How to disable constraints?
Medium
How to disable randomization?
Medium
Difference between static and dynamic casting
Medium
Difference between mailbox and queue
Medium
What is semaphore and in what scenario is it used?
Medium
What is input and output skew in clocking block?
Medium
What are the types of assertions?
Medium
Difference between $strobe, $monitor and $display
Medium
What is ignore bins?
Medium
Difference between ignore and illegal bins.
Medium
How do you define callback?
Medium
What is DPI? Explain DPI export and import.
Medium
What is the implication operator in SVA? Explain its type?
Medium
What all bins are generated by the following code
Medium
What are assertions? Types of assertions?
Medium
What is functional coverage? How is it different from code coverage?
Medium
What is uvm RAL model? why it is required?
Medium
What is the difference between new () and create?
Medium
What is TLM FIFO?
Medium
What is the difference between UVM RAL model backdoor write/read and front door write/read?
Medium
What is objection?
Medium
What is p_sequencer ? OR Difference between m_sequencer and p_sequencer?
Medium
What is the difference between Active mode and Passive mode with respect to agent?
Medium
What is the difference between copy and clone?
Medium
What is UVM factory?
Medium
What are the types of sequencers? Explain each?
Medium
What is virtual sequencer and virtual sequence in UVM?
Medium
How set_config_* works?
Medium
What are the advantages of uvm RAL model?
Medium
Explain end of simulation in UVM?
Medium
What is Virtual interface and how Virtual interface is used?
Medium
Difference between bit [7:0] and byte • Bit is an unsigned 2-state data type that can take only values of either ‘0’ or ‘1’.
Medium
Difference between packed and unpacked array
Medium
Difference between Shallow copy and deep copy
Medium
What is meant by virtual
Medium
What is Polymorphism
Medium
What are Constraints • Constraints are used to restrict the random data generation to meaningful values.
Medium
What is Randomization • Randomization is the process of generating random values to a variable.
Medium
What is Functional coverage • Coverage is a way to measure the quality of testing/verification and completeness.
Medium
What are Assertions
Medium
Arguments to the task are static or dynamic?
Medium
How to get dut ouptut data into the uvm_sequence
Medium
Write a packed array and unpacked array and initialise value and then assign packed array values to unpacked array?
Medium
write a coverage for memory [3:0]
Medium
where monitor connection will happen?
Medium
What is runtime polymorphism?
Medium
What are the UVM factory and its use?
Medium
Why phases are introduced in UVM? What are all phases present in UVM?
Medium
What approach does build_phase use and why?
Medium
Draw and explain the verification environment in UVM.
Medium
What all UVM phases take time?
Medium
What all phases are functions and tasks in UVM?
Medium
Why do we use the super keyword in phases likes super.build_phase, super.main_phase etc?
Medium
Difference between `uvm_do and `uvm_rand_send.
Medium
What are bottom-up and top-down approaches in UVM phases?
Medium
How do uvm_config_db set/get work?
Medium
What is an analysis port?
Medium
What are pre_body and post_body used in sequence?
Medium
What is an active and passive agent?
Medium
Difference between UVM subscriber and UVM scoreboard
Medium
What is uvm objection and why do we need it?
Medium
What are the different ways of exiting the code execution?
Medium
What is a sequence item in UVM?
Medium
Explain how the sequence starts.
Medium
What are lock and grab methods?
Medium
What are the RAL model and its application?
Medium
What do you mean by the front-door and back-door register access?
Medium
What is run_test?
Medium
Explain generalized code structure for UVM monitor and scoreboard.
Medium
Write standard new() function. Since the scoreboard is a uvm_component.
Medium
Implement run_phase to check DUT functionality throughout simulation time.
Medium
What is an in-order and out-of-order scoreboard?
Medium
Do not mix blocking and non-blocking assignments in single always block i.e. For the
Medium
casez: considers all z values as don’t cares. The z can also be specified as ?
Medium
Explain the concept of a flip-flop in Verilog and provide an example of its usage in a real- world application.
Medium
What is the purpose of a testbench in Verilog, and why is it essential during the development process?
Medium
Explain the difference between blocking and non-blocking assignments in Verilog.
Medium
Provide an example of a Verilog module that implements a 4-to-1 multiplexer (MUX) and explain its functionality.
Medium
Explain the purpose of the always block in Verilog and the difference between always @(*) and always @(posedge clk).
Medium
Explain the concept of parameterized modules in Verilog and provide an example.
Medium
What is the purpose of the case statement in Verilog, and how is it used? Provide an example.
Medium
Explain the concept of a finite state machine (FSM) in Verilog and its significance in digital circuit design. Provide a simple example.
Medium
Explain the purpose of the generate construct in Verilog and provide an example of its usage.
Medium
Explain the concept of clock domain crossing (CDC) in Verilog and the challenges associated with it. Provide an example of how to handle CDC.
Medium
Explain the purpose of a Verilog testbench and its role in the hardware design process.
Medium
The following Verilog code is intended to implement a simple 2-to-1 multiplexer. However, it contains a syntax error and does not compile. Identify the error and fix the code. module mux_2to1 (input a, b, sel, output y); assign y = sel ? a : b; endmodule
Medium
The following Verilog code is intended to create a 4-bit counter that counts up on the rising edge of the clock. However, it contains a logical error and does not work as expected. Identify the error and fix the code. module counter_4bit (input clk, input rst, output reg[3:0] count); always @(posedge clk, posedge rst) if (rst) count <= 0; else count <= count + 1; endmodule
Medium
Explain the concept of a finite-state machine (FSM) and its importance in digital circuit design.
Medium
The following Verilog code is intended to implement a 2-bit binary counter with synchronous reset functionality. However, it contains a logical error and does not work as expected. Identify the error and fix the code. module binary_counter_2bit (input clk, input rst, output reg[1:0] count); always @(posedge clk) if (rst) count <= 0; else count <= count + 1; endmodule
Medium
Explain the concept of event-driven simulation in Verilog and its advantages in modeling digital circuits.
Medium
The following Verilog code is intended to implement a 3-input AND gate. However, it contains a syntax error and does not compile. Identify the error and fix the code. module and_gate_3input (input a, b, c, output y); assign y = a && b && c; endmodule
Medium
Explain the concept of RTL (Register-Transfer Level) design in Verilog and its importance in hardware design.
Medium
The following Verilog code is intended to implement a 2-input OR gate. However, it contains a logical error and does not produce the correct output. Identify the error and fix the code. module or_gate_2input (input a, b, output y); assign y = a & b; endmodule
Medium
Explain the concept of a finite-state machine (FSM) in Verilog and provide an example of its practical application.
Medium
The following Verilog code is intended to implement a 4-to-1 multiplexer. However, it contains a syntax error and doesn’t work as expected. Identify the error and fix the code. module mux_4to1(output reg out, input [3:0] data, input [1:0] sel); always @(sel) case(sel) 2'b00: out = data[0]; 2'b01: out = data[1]; 2'b10: out = data[2]; 2'b11: out = data[3]; endcase endmodule
Medium
Explain the concept of blocking and non-blocking assignments in Verilog and when to use each.
Medium
The following Verilog code is intended to implement a 3-bit up-counter. However, it contains a logical error and doesn’t produce the correct count sequence. Identify the error and fix the code. module counter_3bit(output reg [2:0] count, input clk, input reset); always @(posedge clk, posedge reset) if (reset) count <= 3'b0; else count <= count + 1; endmodule
Medium
What is RTL (Register Transfer Level) design in Verilog, and why is it important in hardware description?
Medium
The following Verilog code is intended to implement a 2-input AND gate using assign statements. However, it contains a syntax error and doesn’t work as expected. Identify the error and fix the code. module and_gate(output reg out, input a, input b); assign out reg = a & b; endmodule
Medium
Explain the concept of pipelining in Verilog and its advantages in hardware design.
Medium
The following Verilog code is intended to implement a 2-to-4 decoder using case statements. However, it contains a logical error and doesn’t produce the correct output. Identify the error and fix the code. module decoder_2to4(output reg [3:0] dec_out, input [1:0] select); always @(*) case (select) 2'b00: dec_out = 4'b0001; 2'b01: dec_out = 4'b0010; 2'b10: dec_out = 4'b0100; 2'b11: dec_out = 4'b1000; endcase endmodule
Medium
Explain the concept of Verilog testbenches and their role in the verification process.
Medium
The following Verilog code is intended to implement a 4-bit binary adder. However, it contains a syntax error and doesn’t work as expected. Identify the error and fix the code. module binary_adder(output reg [3:0] sum, input [3:0] a, input [3:0] b); always @(*) sum[3:0] = a[3:0] + b[3:0]; endmodule
Medium
What is the default value of wire and reg?
Medium
Explain Regular delay control, Intra-assignment delay control
Medium
Difference between full and parallel case
Medium
Difference between casex and casez
Medium
What is synchronous and asynchronous reset? Can you explain using DFF and write their Verilog code?
Medium
What is #0 in Verilog and its usage?
Medium
How to generate two different clocks in testbench?
Medium
Design overlapping and non-overlapping FSM for sequence detector 1010.
Medium
Write a Verilog code for D-Latch.
Medium
How can you override the existing parameter value?
Medium
What is Synthesis?
Medium
Write an RTL code to generate 60% duty cycle clock.
Medium
Write an RTL code to generate 100MHz clock.
Medium
Difference between `define and `include.
Medium
What will be output of the following code?
Medium
Why is AHB called a pipelined protocol?
Medium
How does an AHB read transfer work?
Medium
How does an AHB write transfer work?
Medium
What is the difference between HREADY and HREADYOUT?
Medium
How are wait states inserted in AHB?
Medium
What should remain stable when HREADY is LOW?
Medium
What is the difference between NONSEQ and SEQ transfer?
Medium
What are AHB burst transfers?
Medium
What is the role of HSIZE in AHB?
Medium
What is HRESP used for?
Medium
Explain an APB write transfer.
Medium
Explain an APB read transfer.
Medium
How are wait states inserted in APB?
Medium
What should remain stable during APB wait states?
Medium
What is the role of PREADY?
Medium
When is PSLVERR valid?
Medium
What is the use of PSTRB in APB?
Medium
How do back-to-back APB transfers work?
Medium
What is the role of an APB bridge?
Medium
Can AXI VALID wait for READY before asserting?
Medium
Can AXI READY wait for VALID before asserting?
Medium
Why does AXI have separate read and write channels?
Medium
What are outstanding transactions in AXI?
Medium
What is the role of AXI transaction ID?
Medium
What are AxLEN, AxSIZE, and AxBURST?
Medium
What is the purpose of WLAST and RLAST?
Medium
What is the use of WSTRB in AXI?
Medium
What are AXI response types?
Medium
What is the AXI 4KB boundary rule?
Medium
How are unaligned transfers handled in AXI?
Medium
Difference between new[ ] and new()
Medium
Difference between :/ and := operators in randomization
Medium
Is it possible to call a function from constraint? If yes, explain with an example.
Medium
What is the main drawback of an asynchronous reset compared to a synchronous reset?
Hard
When would you choose constrained-random testing over directed testing, and vice versa?
Hard
How does positive clock skew (capture clock later than launch) affect setup and hold?
Hard
Differentiate a deep copy from a shallow copy of a SystemVerilog class object and explain when the distinction bites.
Hard
How does the UVM factory enable overriding a component or object type without editing the testbench, and give a concrete use case?
Hard
What is X-propagation and why can RTL simulation be optimistic about it?
Hard
Differentiate a false path from a multicycle path in STA, with an example of each.
Hard
What are recovery and removal times, and which flop input do they apply to?
Hard
List concrete techniques to close a setup violation on a critical path.
Hard
What is IR drop and how does it interact with timing?
Hard
What are the default values of variables in the SystemVerilog classes?
Hard
What are local and protected access qualifiers?
Hard
How do you implement the randc function in SystemVerilog?
Hard
Is it possible to generate random numbers without using rand or randc keywords?
Hard
Difference between @posedge and $rose?
Hard
Explain the cycle of verification and its closure.
Hard
How will you test the functionality of interrupts using functional coverage?
Hard
What is layered architecture in Verification?
Hard
How can you establish communication between monitor and scoreboard in SystemVerilog?
Hard
Difference between class-based testbench and module-based testbench.
Hard
Difference between p_sequencer and m_sequencer
Hard
What is the virtual sequence? How is it used? Is it necessary to have virtual sequencer for virtual sequence?
Hard
Explain the virtual sequencer and its use.
Hard
What is the UVM barrier and its usage?
Hard
What is the UVM heartbeat and its usage?
Hard
What is SIngleton object and its usage?
Hard
Given an IP, you are the owner of the IP, what are the steps you start with and when will it be signed off?
Hard
Why always block is not used inside a program block?
Hard
What is FIFO? What are underflow and overflow conditions in FIFO?
Hard
What will happen if there is no else part in if-else?
Hard
What is infer latch means? How can you avoid it?
Hard
What is parameter overriding in Verilog?
Hard
Write a Verilog code for 5:1 MUX
Hard
Can you talk about the Verilog event scheduler?
Hard
Difference between dual port ram and FIFO.
Hard
What is `timescale? What does `timescale 1 ns/ 1 ps in a Verilog code?
Hard
What will be the output of m, n, o if c is the clock?
Hard
Convert following decimal numbers in signed binary, octal and hexadecimal numbers using minimum possible number of bits.
Hard
What is the decimal equivalent of hex number 0x3A?
Hard
What is Gray code and what are some of the benefits of using Gray code over Binary code?
Hard
What is a parity bit and how is it computed?
Hard
What are 1's complement and 2's complement? Where are they used?
Hard
What is a BCD code and how is it different from binary code? What will be the BCD and binary code for decimal number 27?
Hard
How can you implement following gates using a 2:1 MUX?
Hard
What are typical uses of (cid:498)XOR(cid:499) gates in data communication?
Hard
When can the output of a 3-input NAND gate be zero?
Hard
How can you design a pass gate or a buffer using XOR gate?
Hard
What will be the output of following gates if one of the inputs is unknown(x)?
Hard
What is the difference between Combinational and Sequential circuits?
Hard
What is the difference between a Multiplexer and Demultiplexer?
Hard
Design a 4:1 MUX using 2:1 multiplexers?
Hard
What is the difference between an encoder and a decoder?
Hard
How is an encoder different from a multiplexer?
Hard
What is a priority encoder and how is it different from a simple encoder?
Hard
What is a ring oscillator? What would be the frequency of a ring oscillator implemented using three NOT gates if each gate has a delay of 2 ps?
Hard
What is the difference between Synchronous and Asynchronous circuits?
Hard
Explain the concept of Setup and Hold times?
Hard
What is meant by clock skew?
Hard
What is the difference between a flip-flop and a latch?
Hard
How can you convert a D Flip-flop to a T Flip-flop?
Hard
Convert a JK flip-flop to D Flip-flop.
Hard
What is difference between a synchronous counter and an asynchronous counter?
Hard
What is the difference between Ripple Carry adder and Carry Look- ahead adder?
Hard
What is the longest path for N-bit ripple carry adder?
Hard
What is the difference between synchronous and asynchronous reset?
Hard
How many flip-flops are needed to implement a 32 bit register?
Hard
What is the difference between a Mealy and a Moore finite state machine?
Hard
What is an Excitation table?
Hard
If given a choice, which flip-flop would you use to implement a synchronous circuit (say a sequence detector)?
Hard
In practice, which flip-flop is used more often for implementing a synchronous circuit? D or JK?
Hard
Design a sequence detector state machine that detects a pattern
Hard
What is the minimum number of flip-flops required to implement a digital synchronous circuit with 9 states?
Hard
Implement following logics using minimum number of D Flip-Flops:
Hard
What is the difference between an ASIC and SOC?
Hard
What are the different steps in a typical ASIC or SOC design flow?
Hard
What is the difference between a RISC and CISC architecture?
Hard
What is the difference between Von-Neumann and Harvard Architecture and which would you prefer?
Hard
Explain the concept of Little Endian and Big Endian formats in terms of memory storage?
Hard
What is the difference between a SRAM and a DRAM?
Hard
A computer has a memory of 256 Kilobytes. How many address bits are needed if each byte location needs to be addressed?
Hard
What are the different types of registers implemented in a CPU?
Hard
Explain the concept of pipelining in computer architecture?
Hard
What is a pipeline hazard? What are the different types of hazards in a pipelined microprocessor design?
Hard
What techniques can be used to avoid each of the 3 types of pipeline hazards - Structural, Data and Control Hazards?
Hard
What are the different types of addressing modes for an instruction?
Hard
What is the principle of spatial and temporal locality of reference?
Hard
What are different kinds of memories in a system?
Hard
What is a cache?
Hard
Give an overview of Cache Operation.
Hard
What is a cache miss or hit condition?
Hard
Will there be a difference in the performance of a program which searches a value in a linked list vs a vector on a machine that has cache memory present?
Hard
What are the different mechanisms used for mapping memory to caches? Compare the advantages and disadvantages of each.
Hard
What's the disadvantage of having a cache with more associativity?
Hard
A 4-way set associative cache has a total size of 256KB. If each cache line is of size 64 bytes, how many sets will be present in the cache?
Hard
What is difference between write-thru and write-back caches? What are the advantages and disadvantages?
Hard
What is the difference between an inclusive and exclusive cache?
Hard
What are the different algorithms used for cache line replacement in a set-way associative cache?
Hard
What is the problem of cache coherency?
Hard
What is the difference between snoop based and directory based cache coherency protocol?
Hard
What is a MESI protocol?
Hard
What is a RFO?
Hard
What is the concept of Virtual memory?
Hard
What is the difference between a virtual memory address and a physical memory address?
Hard
What is the concept of paging?
Hard
What is a TLB (Translation lookaside buffer)?
Hard
What is meant by page fault?
Hard
If a CPU is busy executing a task, how can we stop it and run another task?
Hard
What are interrupts and exceptions and how are they different?
Hard
What is a vectored interrupt?
Hard
What are the different techniques used to improve performance of instruction fetching from memory?
Hard
What is meant by a superscalar pipelined processor?
Hard
What is the difference between in-order and out-of-order execution?
Hard
What is the difference between a conditional branch and unconditional branch instruction?
Hard
What is branch prediction and branch target prediction?
Hard
What is meant by memory mapped I/O?
Hard
What's the advantage of using one-hot coding in design?
Hard
What is the difference between a static and automatic variable, local variable and a global variable in any programming language?
Hard
What do you mean by inline function?
Hard
What is a regular expression?
Hard
What is the difference between a heap and a stack?
Hard
What is the difference between ++a and a++ in any programming language?
Hard
What is meant by memory leak?
Hard
What is the difference between a Compiler and an Interpreter?
Hard
What is the difference between a statically typed language and a dynamically typed language?
Hard
Which of the following is false related to Stack?
Hard
What are the major differences between use and require in Perl?
Hard
What are the pre-processor directives?
Hard
What is the difference between following initializations: int a; and
Hard
What does the keyword volatile mean in C language?
Hard
What is a pointer? Explain the concept of pointer.
Hard
What is the Value and Size of a NULL pointer?
Hard
What is a linked list? How many different types of linked list are there?
Hard
Of what order is the Worst case Time complexity of following algorithms?
Hard
Of what order is the Space complexity of following algorithms?
Hard
Explain the difference between & and && operators in C/C++?
Hard
How does a Structure and a Union differ in terms of memory allocation in C/C++?
Hard
How much memory is allocated for struct ID below?
Hard
How much memory is allocated for union ID below?
Hard
What is a Stack and how does a Stack differ from FIFO?
Hard
What is a kernel?
Hard
What is UNIX and how is it different from Linux?
Hard
Perl is an interpreted language? What does this mean?
Hard
What are different types of data types in Perl?
Hard
What is a Cron Job? When to use a Cron Job?
Hard
What is the use of rsync command in UNIX/Linux?
Hard
What is the use of a \0' character in C/C++?
Hard
What are binary trees?
Hard
How can you generate random numbers in C?
Hard
What are Special Characters, Quantifiers, and Anchors w.r.t regular expressions?
Hard
What is the difference between a class and object?
Hard
What is the difference between a Class and a Struct in C++?
Hard
What is the difference between a Class and a Struct in SystemVerilog?
Hard
What are public, private and protected members?
Hard
What are Method Overriding and Method Overloading? What is the difference between the two?
Hard
What is operator overloading?
Hard
What is a constructor method?
Hard
What is destructor?
Hard
What is the difference between composition and inheritance in OOP?
Hard
What is the difference between a shallow copy and a deep copy used in object oriented programming?
Hard
What are virtual functions in C++ or other OOP languages?
Hard
What is meant by multiple inheritance?
Hard
What is an abstract class?
Hard
What are static methods inside a class?
Hard
What is ‘this pointer with reference to class?
Hard
What is type conversion and type-casting in programming languages?
Hard
How can you find out details regarding what a UNIX/Linux command does?
Hard
Write a UNIX/Linux terminal command: (assume filename = file.txt)
Hard
Write a UNIX/Linux terminal command to display following from a
Hard
Write a UNIX/Linux terminal command to list out names of all files
Hard
Write a UNIX/Linux terminal command to (assume filename = file.txt
Hard
Write a UNIX/Linux command to:
Hard
Mention shell hot keys that does following:
Hard
Write a C code to detect if underlying architecture in a machine is little Endian or big Endian.
Hard
What will be the value of b and c in following code?
Hard
What would be the output of following C program?
Hard
Find the Value of "y" in the following C code:
Hard
What will be the output of the following C program?
Hard
Write a recursive function to find out factorial of a number n where n is always >=0.
Hard
What is the output of this C code when run on a 64-bit machine?
Hard
What is a Linked List and when would you prefer to use linked lists?
Hard
Write a C function to create a singly linked list.
Hard
Write a C function to Insert an Element at the head of a singly linked list.
Hard
Write a C function to Insert an Element at the tail of a singly linked list.
Hard
Write a C function to Insert an Element at position pos in a singly linked list.
Hard
Write a C function to Delete an Element from a singly linked list.
Hard
What will be the output of following Perl code
Hard
What is the importance of using -w and use strict in perl?
Hard
How would you concatenate two strings to form a single string in Perl? Fill in the blank (__?__).
Hard
What is the output of following program?
Hard
Mention different special characters that give a special meaning to the regex search syntax. Explain use of each.
Hard
List some Quantifiers in regular expressions with their use.
Hard
List some Anchors in regular expressions with their use.
Hard
What is the use of the functions chop() and chomp() in Perl?
Hard
What will be the output of the following Perl code?
Hard
What is the difference between blocking and nonblocking assignments in verilog?
Hard
How many flip-flops will be needed when following two codes are synthesized?
Hard
What will be the output of a in below code?
Hard
Write a verilog code to swap contents of two registers (A and B) without any temporary register?
Hard
What is the output of following code?
Hard
What will be the value of c in following cases after sim units?
Hard
Analyze following code and find what is wrong with this code that implements a combinational logic?
Hard
Write a Verilog module for the 3:1 multiplexer that uses the "?:" (conditional operator) A 3:1 multiplexer has 3 input lines, 2 select lines and an output line which is driven by one of input lines based on select inputs.
Hard
What will be the value of X1 and X2 which are modelled using following two always blocks. What is wrong with following coding style?
Hard
What is the difference between synchronous and asynchronous reset and how do we model synchronous and asynchronous reset using verilog code?
Hard
What is the difference between == and === operators?
Hard
Write verilog code for a flip-flop and latch and explain differences?
Hard
Write Verilog code to detect a pattern of 10110 from an input stream of bits.
Hard
Write Verilog code to print nth Fibonacci number where user provides a value for n. Assume n>2.
Hard
Write a Verilog code for Full adder using Half Adder modules.
Hard
What is the difference between a task and a function in verilog?
Hard
What is the difference between a reg, wire and logic in SystemVerilog?
Hard
What is the difference between a bit and logic data type?
Hard
What is the difference between logic[7:0] and byte variable in SystemVerilog?
Hard
Which of the array types: dynamic array or associative array, are good to model really large arrays, say: a huge memory array of 32KB?
Hard
Suppose a dynamic array of integers (myvalues) is initialized to values as shown below. Write a code to find all elements greater than 3 in the array using array locator method (cid:498)find(cid:499)?
Hard
What is the difference between a struct and union in SystemVerilog?
Hard
What is the concept of a ref and const ref argument in SystemVerilog function or task?
Hard
What would be the direction of arguments a and b in following?
Hard
What is the difference between a packed array and an unpacked array?
Hard
What is the difference between a packed and unpacked struct?
Hard
Which of the following statement is true?
Hard
Given a dynamic array of size 100, how can the array be re-sized to hold 200 elements while the lower 100 elements are preserved as original?
Hard
What is the difference between forever and for in SystemVerilog ?
Hard
What is the difference between case, casex and casez in SystemVerilog?
Hard
Which of the logical equality operators == or === are used in case expression conditions for case, casex, and casez?
Hard
What is the difference between $display, $write, $monitor and $strobe in SystemVerilog?
Hard
What is wrong with following SystemVerilog code?
Hard
What is the difference betweennew()andnew[] in SystemVerilog?
Hard
What is the concept of forward declaration of a class in SystemVerilog?
Hard
Analyze following code and explain if there are any issues with code?
Hard
What is the difference between private, public and protected data members of a SystemVerilog class?
Hard
Are SystemVerilog class members public or private by default ?
Hard
What is a nested class and when would you use a nested class?
Hard
What are interfaces in SystemVerilog?
Hard
What is a modport construct in an interface?
Hard
What is a clocking block and what are the benefits of using clocking blocks inside an interface?
Hard
What is the difference between following two ways of specifying skews in a clocking block?
Hard
What are the main regions inside a SystemVerilog simulation time step?
Hard
Given following constraints, which of the following options are wrong?
Hard
Will there be any difference in the values generated in following constraints?
Hard
What is a unique constraint in SystemVerilog?
Hard
How can we disable or enable constraints selectively in a class?
Hard
Given a Packet class with following constraints, how can we generate a packet object with address value greater than 200?
Hard
What arepre_randomize()andpost_randomize() functions?
Hard
Write constraints to generate elements of a dynamic array (abc as
Hard
Write constraints to create a random array of integers such that array size is between 10 and 16 and the values of array are in descending order?
Hard
How can we use constraints to generate a dynamic array with random but unique values ?
Hard
Given a 32 bit address field as a class member, write a constraint to
Hard
What is the difference between hard and soft constraints?
Hard
What will be the value of result printed from each of the threads in below code?
Hard
How many parallel processes does this code generate?
Hard
What is wrong with following SystemVerilog constraint?
Hard
Which keyword in SystemVerilog is used to define Abstract classes?
Hard
What is the difference between a virtual function and a pure virtual function in SystemVerilog?
Hard
What does keyword extends represent in SystemVerilog?
Hard
What are Semaphores? When are they used?
Hard
What are Mailboxes? What are the uses of a Mailbox?
Hard
What is difference between bounded and unbounded mailboxes?
Hard
What is an event in SystemVerilog? How do we trigger an event in SystemVerilog?
Hard
How can we merge two events in SystemVerilog?
Hard
What is std::randomize() method in SystemVerilog and where is it useful?
Hard
Is it possible to override a constraint defined in the base class in a derived class and if so how?
Hard
Identify what could be wrong if following function is called in SystemVerilog constraint as below?
Hard
Is there any difference between following two derived class codes?
Hard
Find issues (if any) in following code?
Hard
Given following definitions of two classes - Packet and Bad Packet, find the correct sequence of which of thecompute_crc() functions gets called in example code?
Hard
Which of following constraint coding (giving same results) is better in terms of performance and why?
Hard
Which of following coding styles are better and why?
Hard
What is wrong in this code?
Hard
What is a virtual interface and where is it used?
Hard
What is the concept of factory and factory pattern?
Hard
What is the concept of callback?
Hard
What is a DPI call?
Hard
What is the difference between DPI import and DPI export?
Hard
What are system tasks and functions? Give some example of system
Hard
What is the difference between directed testing and constrained random verification?
Hard
Explain what are self-checking tests?
Hard
What is Coverage driven verification?
Hard
What is the concept of test grading in functional verification?
Hard
What is Assertion based Verification (ABV) methodology?
Hard
Given a RAM with a single port for read and write - what all conditions need to be verified?
Hard
What is the difference between a single port RAM and dual port RAM?
Hard
What is the difference between an event driven and a cycle based simulator?
Hard
What is a transaction? What are the benefits of Transaction based verification?
Hard
What all simulation/debug tools have you worked on or are you familiar with?
Hard
When do we need reference model for verifying RTL designs? What are the advantages of using reference-models?
Hard
What is a Bus Functional Model?
Hard
How would you track the progress of the verification project? What metrics would you use?
Hard
How do you measure completeness of Verification OR when/how can you say that verification is complete?
Hard
What are Power and Performance Trade-offs?
Hard
What are some of the benefits of UVM methodology?
Hard
What are some of the drawbacks of UVM methodology?
Hard
What is the concept of Transaction Level Modelling?
Hard
What are TLM ports and exports?
Hard
What are TLM FIFOs?
Hard
What is the difference between a get() and peek() operation on a TLM fifo?
Hard
What is the difference between a get() and try_get() operation on a TLM fifo?
Hard
What is the difference between analysis ports and TLM ports? And what is the difference between analysis FIFOs and TLM FIFOs?
Hard
What is the difference between a sequence and sequence item?
Hard
What is the difference between a uvm_transaction and a uvm_sequence_item?
Hard
What is the difference between copy(), clone(), and create() method in a component class?
Hard
Explain the concept of Agent in UVM methodology.
Hard
What all different components can a UVM agent have?
Hard
What is the difference betweenget_name()andget_full_name() methods in a uvm_object class?
Hard
How is ACTIVE agent different from PASSIVE agent?
Hard
How is an Agent configured as ACTIVE or PASSIVE?
Hard
What is a sequencer and a driver, and why are they needed?
Hard
What is the difference between a monitor and a scoreboard in UVM?
Hard
Which method activates UVM testbench and how is it called?
Hard
What steps are needed to run a sequence?
Hard
Explain the protocol handshake between a sequencer and driver?
Hard
What arepre_body()andpost_body()functions in a sequence? Do they always get called?
Hard
Is the start() method on a sequence blocking or nonblocking?
Hard
What are the different arbitration mechanisms available for a sequencer?
Hard
How do we specify the priority of a sequence when it is started on a sequencer?
Hard
How can a sequence get exclusive access to a sequencer?
Hard
What is the difference between a grab() and a lock() on sequencer?
Hard
What is the difference between a pipelined and a non-pipelined sequence-driver model?
Hard
How do we make sure that if multiple sequences are running on a sequencer-driver, responses are send back from driver to the correct sequence?
Hard
What is m_sequencer handle?
Hard
What is a p_sequencer handle and how is it different in m_sequencer?
Hard
What is the difference between early randomization and late randomization while generating a sequence?
Hard
What is a subsequence?
Hard
What is the difference betweenget_next_item()andtry_next_item() methods in UVM driver class?
Hard
What is the difference betweenget_next_item()and get()methods in UVM driver class?
Hard
What is the difference between get() and peek() methods of UVM driver class?
Hard
What is the difference in item_done() method of driver-sequencer API when called with and without arguments?
Hard
Which of the following driver class methods are blocking calls and which are nonblocking?
Hard
Which of the following code is wrong inside a UVM driver class?
Hard
How can you stop all sequences running on a sequencer?
Hard
Which method in the sequence gets called when user calls sequence.print() method?
Hard
What is a virtual sequence and where do we use a virtual sequence?
Hard
What is the difference between creating an object using new() and create() methods?
Hard
How do we register an uvm_component class and uvm_sequence class with factory?
Hard
Why should we register a class with factory?
Hard
What is meant by factory override?
Hard
What is the difference between instance override and type override?
Hard
Can instance override and type override be used for both UVM_component class and transaction types ?
Hard
What is the concept of objections and where are they useful?
Hard
How can we implement a simulation timeout mechanism in UVM methodology?
Hard
What is the concept of phasing in UVM methodology?
Hard
What are the different phases of a UVM component? What are the sub-phases for the UVM run_phase()?
Hard
Why is build_phase() executed top down in uvm_component hierarchy?
Hard
What is the use of phase_ready_to_end() method in a uvm_component class?
Hard
What is uvm_config_db and what is it used for?
Hard
How do we use the get() and set() methods of uvm_config_db?
Hard
Is it possible for a component lower in testbench hierarchy to pass a handle to a component in higher level of hierarchy using get/set config methods?
Hard
What is the recommended way of assigning virtual interfaces to different components in a UVM verification methodology?
Hard
Explain how simulation ends in UVM methodology?
Hard
What is UVM RAL (UVM Register Abstraction Layer)?
Hard
What is UVM Call back?
Hard
What is uvm_root class?
Hard
What is the parent class for uvm_test?
Hard
What is Formal Verification?
Hard
Is Formal Verification a Static Verification process or a Dynamic Verification process?
Hard
What are the different methods for performing Formal Verification?
Hard
Describe Model Checking.
Hard
Describe Formal Equivalence.
Hard
What are the advantages of Formal Verification over Dynamic Verification?
Hard
What are limitations of Formal Verification?
Hard
What are the main components of the power consumption in a CMOS circuit?
Hard
What is Dynamic Power and what all parameters does Dynamic Power consumption depend upon?
Hard
What is Static Power and what all parameters does Static Power consumption depend upon?
Hard
Explain the concept of Multi-Voltage domains and why is it needed?
Hard
What is Dynamic Voltage Frequency Scaling DVFS and when is it used?
Hard
What is Power Aware Simulation and why is it important?
Hard
What is meant by a Power Domain?
Hard
What is the need of having level shifters in a design?
Hard
Define the concept of Isolation with respect to Power Domains.
Hard
What is meant by metastability? When does it happen and what are its consequences?
Hard
How can metastability be avoided?
Hard
How does a basic synchronizer circuit look like? Draw a sample
Hard
What is Clock Gating?
Hard
What is Power Gating and why is it used?
Hard
What kind of issues can be encountered in designs (having multiple Clock Domains) at Clock Domain Crossings (CDC)?
Hard
How can you synchronize signal(s) between two clock domains?
Hard
Give an example of an issue that can occur while transferring data from a faster clock domain to a slower clock domain.
Hard
What are the advantages and disadvantages of using an Asynchronous Reset?
Hard
What are the advantages and disadvantages of using a Synchronous Reset?
Hard
What is a Reset Recovery Time? Why is it relevant?
Hard
What is a frequency synthesizer? Give an example of frequency synthesizer?
Hard
What is a PLL?
Hard
Draw a block diagram depicting the use of PLL as a frequency synthesizer?
Hard
What are the different types of code coverage?
Hard
During a project if we observe high functional coverage (close to 100%) and low code coverage (say < 60%) what can be inferred?
Hard
During a project if we observe high code coverage (close to 100%) and low functional coverage (say < 60%) what can be inferred?
Hard
What are the two different types of constructs used for functional coverage implementation in SystemVerilog?
Hard
Can covergroups be defined and used inside classes?
Hard
What are coverpoints and bins?
Hard
How many bins are created in following examples for coverpoint cp_a ?
Hard
What is the difference between ignore bins and illegal bins?
Hard
How can we write a coverpoint to look for transition coverage on an expression?
Hard
What are the transitions covered by following coverpoint?
Hard
What does following bin try to cover?
Hard
What are wildcard bins?
Hard
What is cross coverage? When is cross coverage useful in Verification?
Hard
How many bins are created by following cross coverage?
Hard
What can be wrong with following coverage code?
Hard
What are the different ways in which a covergroup can be sampled?
Hard
How can we pass arguments to a covergroup and when will that be useful?
Hard
Can coverpoints inside a covergroup reference hierarchical signals in a design?
Hard
Can we have cross coverage between coverpoints in different covergroups?
Hard
What is the difference between coverage per instance and per type?
Hard
What is an assertion and what are the benefits of using assertions in Verification?
Hard
What are different types of assertions?
Hard
What are the differences between Immediate and Concurrent assertions?
Hard
What is the difference between simple immediate assertion and deferred immediate assertions?
Hard
What are the advantages of writing a checker using SVA
Hard
What are the different ways to write assertions for a design unit?
Hard
What is a sequence as used in writing SystemVerilog Assertions?
Hard
When does following sequence evaluate to true?
Hard
Can a sequence be declared in?
Hard
Is it possible to have concurrent assertions implemented inside a class?
Hard
Explain when the following sequence matches?
Hard
What is a sequence repetition operator? What are the three different type of repetition operators used in sequences?
Hard
Find any issue (not syntax errors) with following assertion?
Hard
What is an implication operator?
Hard
What is the difference between an overlapping and nonoverlapping implication operator?
Hard
Can implication operator be used in sequences?
Hard
Is nested implication allowed in SVA?
Hard
What does the system task $past() do?
Hard
Write an assertion to make sure that the state variable in a state machine is always one hot value.
Hard
Whats the difference between assert and assume directives in SystemVerilog?
Hard
What is bind construct used in SystemVerilog for?
Hard
How can all assertions be turned off during simulation?
Hard
What are the different ways in which a clock can be specified to a property used for assertion?
Hard
What is a Version Control System?
Hard
What is the need of a Version Control System?
Hard
What are some examples of Version Control Systems?
Hard
What is a repository?
Hard
How to add a new file or directory in the CVS database?
Hard
How to check-in a file to a CVS database?
Hard
How to check out a file from CVS Database?
Hard
How to update files in your working environment to the latest in CVS database?
Hard
What is tagging and how to tag a file?
Hard
How to check-out a set of files (in a module) from a given tag?
Hard
How can you delete a tag?
Hard
How to find difference between files from two different versions?
Hard
How can you see the check-in log messages for a file?
Hard
How can you check the status of a file?
Hard
How can you view the tag information with the status of a file?
Hard
Whats the advantage of using GIT over CVS?
Hard
What would git command git init do?
Hard
What git command is used to create a git repo for your personal changes/development?
Hard
Which command is used to fetch the latest updates from other repositories?
Hard
Where does git keep track of what version you have checked out?
Hard
How do you rename a file in GIT?
Hard
What is "branch" , "Tag" and "Trunk" in SVN?
Hard
What is the difference between Update and Commit?
Hard
What is the SVN command to add a file or dir?
Hard
What does the result codes G and R in SVN indicates?
Hard
What is the command to create a new tag from the trunk?
Hard
What is the function of Revert in subversion?
Hard
Implement following digital gates ONLY using mathematical
Hard
Two bulbs of 10W and 100W are connected in series with an AC power supply of 100V. Which bulb will glow brighter and why?
Hard
Find out the next term in the series: F13, S15, T17, T19, S21, M23, __?
Hard
There is a triangle and on it are 3 ants, one on each corner, and they are free to move along the sides of the triangle. What is probability that the ants will collide?
Hard
How could a baby fall out of a 27 story building on the ground and live?
Hard
Where all (What all organizations) have you applied for a job in addition to our organization?
Hard
Why does an AHB ERROR response take two cycles?
Hard
How should a manager behave after an AHB ERROR response?
Hard
What is the AHB 1KB boundary rule?
Hard
What is a BUSY transfer and why is it used?
Hard
What is a locked transfer in AHB?
Hard
What is the role of arbitration in AHB?
Hard
What should be verified in an AHB-to-APB bridge?
Hard
What are common AHB protocol assertions?
Hard
How would you debug an AHB data mismatch?
Hard
Can PENABLE be asserted in the same cycle as PSEL?
Hard
What happens if PREADY remains LOW for multiple cycles?
Hard
Can PSLVERR be sampled when PREADY is LOW?
Hard
If an APB write returns PSLVERR, should the register update happen?
Hard
What APB assertions are commonly written?
Hard
How should unaligned or narrow APB accesses be handled?
Hard
How would you debug an APB read data mismatch?
Hard
Can AXI write data arrive before write address?
Hard
When can BVALID be asserted?
Hard
When can RVALID be asserted?
Hard
Why must VALID not depend on READY?
Hard
How does AXI handle write data ordering?
Hard
Does AXI support early burst termination?
Hard
What is the difference between SLVERR and DECERR?
Hard
What is the effect of register slices in AXI?
Hard
What AXI assertions are commonly written?
Hard
How would you debug an AXI hang?
Hard
What functional coverage is useful for AXI verification?
Hard
How will be your approach if code coverage is 100% but functional coverage is too low?
Hard
How will be your approach if functional coverage is 100% but code coverage is too low?
Hard
What is FIFO? What are underflow and overflow conditions in FIFO? Write Verilog code for the design.
Hard
What are all different applications of FIFO?
Hard
Swap register content with and without using an extra register.
Hard
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