Interview process

1. 1

   Hiring manager round

   45–60 min · hiring manager

   Resume-led screen that also samples the ML + hardware blend

   What they ask

   • Walk through your resume, then an ML project you owned (~70–80%)
   • Your specific role and responsibilities versus the team's
   • A quick ML or Python question (~10%)
   • One or two behavioral prompts — ownership, deadlines (~10%)
2. 2

   ML fundamentals & coding round

   45–60 min · video + coding pad≈30% weight

   Core ML and Python

   What they ask

   • Bias/variance and the right metric per problem
   • Overfitting controls and validation
   • A Python or data problem on a shared pad
   • Feature engineering choices
3. 3

   ML-for-EDA & systems round

   45–60 min · onsite panel≈30% weight

   Applied modeling in a chip flow

   What they ask

   • Predict congestion or timing from design data
   • RL for placement or test generation
   • LLMs for RTL/DV assistance
   • A data pipeline from EDA logs and deployment
4. 4

   Resume-based round

   45–60 min · onsite panel≈20% weight

   Deep dive on a model with real impact

   What they ask

   • End-to-end walkthrough of a project you owned
   • Dataset and evaluation design
   • A model that moved a real metric
   • Trade-offs and decisions you made
5. 5

   Behavioral round

   45 min · hiring manager / peer panel≈20% weight

   Cross-discipline impact

   What they ask

   • An ML win on real data
   • Working with design and verification teams
   • A deadline you protected
   • Thoughtful questions for the team

How to prepare

• Resume stories: rehearse an ML project end to end and lead with your own role, not the team's.
• Fundamentals: solidify bias/variance, the right metric per problem, and overfitting controls.
• Coding: be comfortable coding data transforms and a simple model in Python.
• Applied: have an opinion on where ML actually helps EDA (congestion, timing, test-gen).
• Impact: prepare a project where your model moved a real metric.

Practice these sub-domains

Drill leveled questions for each area of the AI/ML for Chip Design & DV Automation loop.