Interview Questions
Design Verification
SystemVerilog, UVM, coverage & testbench architecture
Interview process
A DV loop opens with a resume-led hiring-manager round, then four technical rounds that weight live coding, UVM methodology, project depth, and behavioral signal. Coding and methodology carry the most weight (~60% combined), so a clean SystemVerilog/UVM coding pad and story-ready projects both matter.
Design Verification study plans
Hands-on, week-by-week assignments that turn these topics into working RTL and testbenches.
Question bank by sub-domain
Pick a sub-domain to study leveled questions, each tagged with the companies that ask it.
Digital Fundamentals
Logic, FSMs, timing basics that every DV screen assumes
Verilog
RTL & testbench constructs, event scheduling, races
SystemVerilog
OOP, randomization, interfaces, mailboxes, fork/join
UVM
Components, phases, sequences, factory, RAL, TLM
Assertions (SVA)
Immediate & concurrent assertions, sequences, properties
Functional Coverage
Covergroups, bins, cross coverage, closure
Verification Concepts
Planning, CRV, scoreboards, reference models
Bus Protocols
AXI / AHB / APB, PCIe, handshakes, ordering
Scripting
Perl / Python / Makefiles / regression flow
C / C++
Pointers, memory, DPI-C, reference models
Clock Domain Crossing
Metastability, synchronizers, gray-code FIFOs, reset
Debug & Methodology
Triage, waveform debug, regressions, seeds
Go deeper
Study the concepts behind these questions, then follow a week-by-week plan.
Design Verification interview roadmap
3 months · 12 checkable tasks
Follow the planGuide · 9 minUVM Testbench Architecture: A Complete Walkthrough
How a UVM testbench is built end to end — test, environment, agent, sequencer, driver, monitor, scoreboard and coverage — with a diagram, code and the questions interviewers ask.