Interview Questions
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Background and fit
- 2Technical phone screen
DFT/validation or process fundamentals
- 3Onsite: test & yield
Test flows, failure analysis, yield reasoning
- 4Onsite: debug
Structured debug and trade-offs
- 5Hiring manager & behavioral
STAR stories, project deep-dive, team fit and salary discussion
Free sample questions
3 freeQ1
Medium
DFT
What does test compression (e.g., EDT) buy you, and what is the trade-off?
Answer
Compression drives many internal scan chains from a few external channels via a decompressor, and compacts responses via a compactor — cutting test data volume and test time by 10–100×. The trade-off is reduced observability from aggregation (X-masking needed), added logic, and some coverage/diagnosis complexity.
Compression ratio vs coverage/diagnosis is the classic DFT trade discussion.
Q2
Hard
PD + STA
Differentiate a false path from a multicycle path in STA, with an example of each.
Answer
A false path is a topological path that never propagates a real transition of interest (e.g., a path between two asynchronous clock domains, or a test-only path) — it's excluded from timing. A multicycle path is real but is allowed more than one clock cycle to propagate (e.g., a slow datapath whose result is captured every 2 cycles), so setup is relaxed to N cycles.
A common trap is setting a setup multicycle without the corresponding hold adjustment.
Q3
Easy
DFT
The stuck-at fault model assumes a faulty node is:
- Randomly toggling
- Permanently held at logic 0 or logic 1
- Slow to transition
- Shorted to a neighbor
Stuck-at-0 / stuck-at-1 models a node permanently tied to a logic value. It's simple and effective; transition and bridging fault models capture other defects.
Full question bank
317 lockedHow does dynamic switching power scale with supply voltage V?
Easy
What does clock tree synthesis (CTS) accomplish?
Easy
In a timing report, what does negative slack indicate?
Easy
Difference between byte a and bit [7:0] a.
Easy
What are pass-by-value and pass-by-reference methods?
Easy
Difference between === and == operators?
Easy
Difference between initial and final block.
Easy
Write rand constraint on a 3 bit variable with distribution 60% for 0 to 5 and 40% for 6,7. Write coverpoint for the same.
Easy
Difference between uvm_object and uvm_component
Easy
Difference between uvm_transaction and uvm_sequence_item
Easy
Difference between copy and clone.
Easy
What is severity and verbosity in UVM?
Easy
Difference between sequence and sequencer.
Easy
How is scoreboard connected to different components?
Easy
Difference between blocking and non-blocking assignments
Easy
Difference between wire and reg
Easy
Explain the difference between a static and automatic function with example.
Easy
Difference between $stop and $finish.
Easy
What is AHB and why is it used?
Easy
Where is AHB normally used in an SoC?
Easy
What is the difference between AHB and APB?
Easy
Which peripherals are commonly connected to APB?
Easy
What are the phases of an APB transfer?
Easy
What is the difference between PSEL and PENABLE?
Easy
What is AXI and why is it used?
Easy
What is the VALID/READY handshake in AXI?
Easy
What is a scan chain and why is it inserted?
Medium
Define controllability and observability in the context of testability.
Medium
What is the difference between clock gating and power gating?
Medium
Multi-Vt cell libraries let a designer:
Medium
What is the antenna effect, and name one fix.
Medium
High placement congestion most directly harms:
Medium
Define setup time and hold time, and describe what a hold violation implies about a path.
Medium
A hold-time violation is correctly fixed by:
Medium
What is the difference between pre-silicon and post-silicon validation?
Medium
What does a shmoo plot show?
Medium
Why are decoupling capacitors placed close to a chip's power pins?
Medium
What is crosstalk, and name one way to reduce it.
Medium
An unterminated fast transmission line most directly causes:
Medium
Which fault model targets timing-related (slow-to-switch) defects?
Medium
Write a constraint to generate unique values in rows for a multidimensional array.
Medium
Write a constraint to generate an address where 9 bits are always set to 1, and sequences of 111 or 000 should not occur in a 16-bit address.
Medium
Write a Constraint to generate a pattern 5,-10,15,-20,25.....
Medium
Write a constraint to generate the Fibonacci series.
Medium
Write a constraint to generate palindrome.
Medium
Write a constraint to generate a pattern of 000111222333444555...
Medium
Write an SV constraint to make diagonal elements Zero.
Medium
Derive odd numbers within the range of 10 to 30 using SV constraint.
Medium
Can you provide a code example of how to use constraints to access a single bit of a 16-bit variable?
Medium
Give an example for Non-weighted code?
Medium
In how many different ways can number 5 be represented using 2-4-2-1 code?
Medium
What are all the BCD numbers that can be uniquely represented in 2-4-2-1 weighted code?
Medium
What is the condition for a weighted code to be self-complementary?
Medium
Convert the Gray code number 11001 to binary code?
Medium
Represent 45 in the number systems (a) binary (b) BCD (c) Excess-3 (d) Gray code
Medium
What will be the result if all the zeros are retained from LSB side until 1 is seen, including that 1, and complement all the following bits of a binary number?
Medium
Explain the detailed procedure for BCD addition?
Medium
Which gates are called universal gates? Why?
Medium
In how many ways can a NAND gate be converted into an inverter? Show all the possibilities?
Medium
Give implementation of XOR using minimum number of NAND gates?
Medium
Explain parity generation and its significance?
Medium
Give a circuit for 4-bit even parity checker? And explain the same how can it be reused for parity generation?
Medium
How to obtain the dual of a Boolean equation?
Medium
Generalization of Q13: The grouping of k adjacent cells, in a N variable K-Map will lead to a term of ----- literals?
Medium
(a) Expand the Boolean function f(x,y,z) = x’z’ + xy + xz in terms of x? (b) Implement f using a 2:1 Mux and external gates?
Medium
You are given a 2:4 decoder, a 2 input OR gate and a 3 input OR gate. Using these components design a system which takes A & B as inputs and generates the following four outputs: AB, (AB)' , A+B, (A+B)'.
Medium
Design "OR" gate using HA's?
Medium
Design a full adder using half-adders and minimum number of external gates?
Medium
Compare the two implementations of Q15.
Medium
If each XOR gate has a propagation delay of 10ns and AND/OR gate has a delay of 5ns each (irrespective of number of inputs), what is the total propagation delay in adding two 4 bit numbers in case of (a) Normal full adder (b) Carry Look Ahead adder.
Medium
There is a sixteen bit adder with ripple carry. Which of the following gives minimum delay for the output? (Fastest output) F0 + F1, FF + FF, FF + F1
Medium
Design a subtractor unit using a 4-bit comparator, 4-bit binary adder and some external gates, which performs A-B if A>B and else B-A. A and B are two 4-bit binary numbers.
Medium
Use the above designed circuit as block box and give a scheme for finding the absolute value of a 4-bit number?
Medium
Design a circuit that generates 9’s compliment of a BCD digit using binary adder?
Medium
You have three delay elements D1, D2, D3 that delay a clock by 25%,50% and 75% respectively. Design a frequency doubling (fout = 2 * fin) circuit that uses these delay elements along with any combinational logic.
Medium
Mention two basic applications of flip-flops?
Medium
Implement S-R Latch with control input using 2-input NAND gates?
Medium
Give the characteristic table and characteristic equation for J-K Flip-flop?
Medium
Construct a J-K flip flop using a DFF, 2:1 Mux and an-inverter?
Medium
In C-N (Change-No change) flip flop, there won’t be any change in output as long as N is 0, irrespective of C. If N=1, then if C = 0 output will change to zero else if C =1 output will be the compliment of previous output. (a) Write the characteristic table ? (b) Design this using J-K flip-flop?
Medium
Give the state transition diagram for J-K flip flop?
Medium
Which of the following flip flops can work at maximum frequency?
Medium
The following digital circuit shows two flops with a logic delay (dly1) in between and two clock buffer delays (dly2, dly3). Derive the conditions in terms of (dly1,dly2,dly3) to fix setup and hold timing violations at the input of second FF? Tcq – Clock to Q delay, Tsu -- Setup time and Th – hold time.
Medium
Design a 4-bit binary counter using TFFs?
Medium
How do you change the above design to get (a) 66.67% duty cycle (b) 50% duty cycle?
Medium
Design the Digital Circuit which gives fout = (2/3) fin
Medium
The following FSM shows the zero circulating ring counter. Predict the values of the missing states?
Medium
What is the output frequency of a 4-bit binary counter for an input clock of 160 MHz?
Medium
Design a counter using DFF that counts in the sequence: 0,4,2,7,0,4,2,7,0,4……?
Medium
Using external gates and 4-bit counter, design a circuit which gives ‘1’ if the number of clocks are multiples of 4.
Medium
What are the frequencies F1, F2, F3 and F4 after each stage if an input clock of 10MHz is applied?
Medium
Define : (a) Test Pattern/Test set (b) ATPG
Medium
Explain the procedure for detecting a specific fault in a given circuit?
Medium
Give the test patterns that are needed to verify all the stuck at problems of a (a) 2- Input NAND Gate (b) 3-input NAND Gate
Medium
(a) Give the circuit for a 4-bit parity generator? (b) Derive the minimal test set that can detect all stuck-at-faults?
Medium
Give the characteristics of Static-zero Hazard?
Medium
Find a hazard-free minimum cost implementation of the function: F(A,B,C,D) = ∑ (0,4,11,13,15) + d(2,3,5,10)
Medium
What are the advantages and disadvantages of CMOS logic?
Medium
Show the circuit for CMOS inverter and explain the basic operation?
Medium
Find out fan_out and propagation delay of a logical gate for which the following specifications are given: VCC = 5V, ICCH = 1mA, ICCL = 2mA, IOH = 1mA, IOL = 20mA, IIH = 0.05mA and IIL = 2mA
Medium
How many minimum number of MOS transistors are required to implement a Full Adder using CMOS technology?
Medium
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
Medium
Show the circuit of Transmission gate and explain the functionality?
Medium
Why don’t we use just one NMOS or PMOS in a transmission gate?
Medium
The output and input of a static CMOS inverter are connected as shown in the above figure. What is the output voltage?
Medium
What are the applications of open-collector gate?
Medium
Differentiate between RAM and ROM?
Medium
How many number of 16X8 size memories are needed to obtain a memory of size 256X16?
Medium
Draw the circuit for SRAM?
Medium
Explain read-refresh operation in case of DRAM?
Medium
Expand the following: (a) PLD (b) PLA (c) PAL (d) FPGA
Medium
What is the difference between PLA and PAL?
Medium
In a particular system, the sender sends data at the rate of 80 words / 100 clocks and the receiver can consume at the rate of 8 words / 10 clocks. Calculate the depth of FIFO so that no data is dropped under following assumptions: - There is no feedback or handshake mechanism. - Occurrence of data in that time period is guaranteed but exact place in those clock cycles is indeterminate.
Medium
What is the difference between code coverage and functional coverage?
Medium
What is the difference between a passive monitor and an active monitor?
Medium
How are test cases included in the simulation environment?
Medium
What are the different ways test cases are included for simulations?
Medium
Explain some coding guidelines that you followed in your environment?
Medium
In a packet protocol, where is the packet comparison done?
Medium
Explain the concept of subroutines in Perl. What are subroutines, and how are they used in Perl programming? Provide an example demonstrating the usage of subroutines.
Medium
Explain the concept of file handling in Perl. How can you open, read, write, and close files in Perl? Provide an example demonstrating file operations.
Medium
Explain the concept of references in Perl. What are references, and how are they used in Perl programming? Provide an example demonstrating the usage of references.
Medium
Explain the concept of closures in Perl. What are closures, and how are they used in Perl programming? Provide an example demonstrating the usage of closures.
Medium
Explain the concept of source filters in Perl. What are source filters, and how are they used in Perl programming? Provide an example demonstrating the usage of source filters.
Medium
Write an assertion check to make sure that a signal is high for a minimum of 2 cycles and a maximum of 6 cycles.
Medium
Write an assertion checker to make sure that an output signal never goes X?
Medium
Write an assertion to check divide by 2 circuit output.
Medium
Whenever valid signal goes high enable signal should be asserted in the next cycle & it
Medium
Whenever the signal A goes high from the next cycle the signal B should repeat n no. of times, where n is equal to value of bit[3:0]C when signal A is asserted.
Medium
Write a SystemVerilog code to identify and display numbers divisible by 8 within the range of 0 to 100?
Medium
Difference between fork-join, fork-join_any, and fork-join_none
Medium
Difference Between always_comb and always@(*)?
Medium
Difference between static and automatic functions
Medium
Difference between shallow and deep copy
Medium
What are the ‘super’ and ‘this’ keywords in SystemVerilog?
Medium
What is polymorphism and its advantages?
Medium
What is the use of a scope resolution operator?
Medium
Difference between virtual and pure virtual function
Medium
What is a virtual interface and its need?
Medium
What is a virtual class?
Medium
What are pre_randomize and post_randomize methods?
Medium
How to disable randomization?
Medium
Difference between mailbox and queue
Medium
What is semaphore and in what scenario is it used?
Medium
What is ignore bins?
Medium
Difference between ignore and illegal bins.
Medium
How do you define callback?
Medium
What is DPI? Explain DPI export and import.
Medium
What is the implication operator in SVA? Explain its type?
Medium
What all bins are generated by the following code
Medium
What is the difference between UVM RAL model backdoor write/read and front door write/read?
Medium
What is UVM factory?
Medium
What is Virtual interface and how Virtual interface is used?
Medium
Difference between Shallow copy and deep copy
Medium
How to get dut ouptut data into the uvm_sequence
Medium
What is runtime polymorphism?
Medium
What are the UVM factory and its use?
Medium
Difference between UVM subscriber and UVM scoreboard
Medium
What are the different ways of exiting the code execution?
Medium
What is run_test?
Medium
Implement run_phase to check DUT functionality throughout simulation time.
Medium
What is an in-order and out-of-order scoreboard?
Medium
Explain the difference between blocking and non-blocking assignments in Verilog.
Medium
Explain the concept of parameterized modules in Verilog and provide an example.
Medium
What is the purpose of the case statement in Verilog, and how is it used? Provide an example.
Medium
Explain the concept of clock domain crossing (CDC) in Verilog and the challenges associated with it. Provide an example of how to handle CDC.
Medium
Explain the purpose of a Verilog testbench and its role in the hardware design process.
Medium
The following Verilog code is intended to implement a simple 2-to-1 multiplexer. However, it contains a syntax error and does not compile. Identify the error and fix the code. module mux_2to1 (input a, b, sel, output y); assign y = sel ? a : b; endmodule
Medium
The following Verilog code is intended to create a 4-bit counter that counts up on the rising edge of the clock. However, it contains a logical error and does not work as expected. Identify the error and fix the code. module counter_4bit (input clk, input rst, output reg[3:0] count); always @(posedge clk, posedge rst) if (rst) count <= 0; else count <= count + 1; endmodule
Medium
Explain the concept of a finite-state machine (FSM) and its importance in digital circuit design.
Medium
Explain the concept of pipelining in Verilog and its advantages in hardware design.
Medium
The following Verilog code is intended to implement a 4-bit binary adder. However, it contains a syntax error and doesn’t work as expected. Identify the error and fix the code. module binary_adder(output reg [3:0] sum, input [3:0] a, input [3:0] b); always @(*) sum[3:0] = a[3:0] + b[3:0]; endmodule
Medium
Difference between full and parallel case
Medium
Write an RTL code to generate 60% duty cycle clock.
Medium
Difference between `define and `include.
Medium
How does an AHB write transfer work?
Medium
What should remain stable when HREADY is LOW?
Medium
What is the role of HSIZE in AHB?
Medium
When is PSLVERR valid?
Medium
How do back-to-back APB transfers work?
Medium
What is the purpose of WLAST and RLAST?
Medium
What is the AXI 4KB boundary rule?
Medium
Difference between :/ and := operators in randomization
Medium
Is it possible to call a function from constraint? If yes, explain with an example.
Medium
How does positive clock skew (capture clock later than launch) affect setup and hold?
Hard
What are recovery and removal times, and which flop input do they apply to?
Hard
List concrete techniques to close a setup violation on a critical path.
Hard
What is IR drop and how does it interact with timing?
Hard
Explain the cycle of verification and its closure.
Hard
How will you test the functionality of interrupts using functional coverage?
Hard
How can you establish communication between monitor and scoreboard in SystemVerilog?
Hard
What is the UVM heartbeat and its usage?
Hard
What is SIngleton object and its usage?
Hard
Why always block is not used inside a program block?
Hard
What will happen if there is no else part in if-else?
Hard
What is infer latch means? How can you avoid it?
Hard
Write a Verilog code for 5:1 MUX
Hard
What is Gray code and what are some of the benefits of using Gray code over Binary code?
Hard
What will be the output of following gates if one of the inputs is unknown(x)?
Hard
What is the difference between Combinational and Sequential circuits?
Hard
What is a ring oscillator? What would be the frequency of a ring oscillator implemented using three NOT gates if each gate has a delay of 2 ps?
Hard
What is the difference between Synchronous and Asynchronous circuits?
Hard
Explain the concept of Setup and Hold times?
Hard
What is the difference between synchronous and asynchronous reset?
Hard
How many flip-flops are needed to implement a 32 bit register?
Hard
In practice, which flip-flop is used more often for implementing a synchronous circuit? D or JK?
Hard
Design a sequence detector state machine that detects a pattern
Hard
Explain the concept of Little Endian and Big Endian formats in terms of memory storage?
Hard
What are the different types of registers implemented in a CPU?
Hard
What are the different mechanisms used for mapping memory to caches? Compare the advantages and disadvantages of each.
Hard
What's the disadvantage of having a cache with more associativity?
Hard
What is the difference between snoop based and directory based cache coherency protocol?
Hard
What is the concept of Virtual memory?
Hard
What are the different techniques used to improve performance of instruction fetching from memory?
Hard
What is meant by a superscalar pipelined processor?
Hard
What is the difference between in-order and out-of-order execution?
Hard
What is the difference between a conditional branch and unconditional branch instruction?
Hard
What is branch prediction and branch target prediction?
Hard
What's the advantage of using one-hot coding in design?
Hard
What is the difference between a heap and a stack?
Hard
What is the Value and Size of a NULL pointer?
Hard
Explain the difference between & and && operators in C/C++?
Hard
How much memory is allocated for union ID below?
Hard
What is a Stack and how does a Stack differ from FIFO?
Hard
What are different types of data types in Perl?
Hard
What are Special Characters, Quantifiers, and Anchors w.r.t regular expressions?
Hard
What is the difference between a Class and a Struct in SystemVerilog?
Hard
What is operator overloading?
Hard
What is destructor?
Hard
What is meant by multiple inheritance?
Hard
What is ‘this pointer with reference to class?
Hard
Write a UNIX/Linux terminal command: (assume filename = file.txt)
Hard
What would be the output of following C program?
Hard
What is the output of this C code when run on a 64-bit machine?
Hard
Write a C function to create a singly linked list.
Hard
List some Quantifiers in regular expressions with their use.
Hard
List some Anchors in regular expressions with their use.
Hard
What is the difference between blocking and nonblocking assignments in verilog?
Hard
How many flip-flops will be needed when following two codes are synthesized?
Hard
Analyze following code and find what is wrong with this code that implements a combinational logic?
Hard
Write a Verilog module for the 3:1 multiplexer that uses the "?:" (conditional operator) A 3:1 multiplexer has 3 input lines, 2 select lines and an output line which is driven by one of input lines based on select inputs.
Hard
Write Verilog code to print nth Fibonacci number where user provides a value for n. Assume n>2.
Hard
What is the difference between a reg, wire and logic in SystemVerilog?
Hard
What is the difference between a bit and logic data type?
Hard
Suppose a dynamic array of integers (myvalues) is initialized to values as shown below. Write a code to find all elements greater than 3 in the array using array locator method (cid:498)find(cid:499)?
Hard
What is the difference between a struct and union in SystemVerilog?
Hard
What is the concept of a ref and const ref argument in SystemVerilog function or task?
Hard
What would be the direction of arguments a and b in following?
Hard
What is the difference between a packed array and an unpacked array?
Hard
Which of the following statement is true?
Hard
What is the difference between case, casex and casez in SystemVerilog?
Hard
What is the difference between $display, $write, $monitor and $strobe in SystemVerilog?
Hard
What is the difference between private, public and protected data members of a SystemVerilog class?
Hard
Are SystemVerilog class members public or private by default ?
Hard
Will there be any difference in the values generated in following constraints?
Hard
What arepre_randomize()andpost_randomize() functions?
Hard
Which keyword in SystemVerilog is used to define Abstract classes?
Hard
Identify what could be wrong if following function is called in SystemVerilog constraint as below?
Hard
Is there any difference between following two derived class codes?
Hard
Find issues (if any) in following code?
Hard
Given following definitions of two classes - Packet and Bad Packet, find the correct sequence of which of thecompute_crc() functions gets called in example code?
Hard
Which of following coding styles are better and why?
Hard
Explain what are self-checking tests?
Hard
What is the concept of test grading in functional verification?
Hard
Given a RAM with a single port for read and write - what all conditions need to be verified?
Hard
What is the difference between a single port RAM and dual port RAM?
Hard
What is a transaction? What are the benefits of Transaction based verification?
Hard
What are Power and Performance Trade-offs?
Hard
What are some of the drawbacks of UVM methodology?
Hard
What is the difference between a get() and try_get() operation on a TLM fifo?
Hard
What is the difference between copy(), clone(), and create() method in a component class?
Hard
Explain the concept of Agent in UVM methodology.
Hard
What is the difference between a monitor and a scoreboard in UVM?
Hard
What steps are needed to run a sequence?
Hard
Is the start() method on a sequence blocking or nonblocking?
Hard
What is the difference between a pipelined and a non-pipelined sequence-driver model?
Hard
What is a subsequence?
Hard
Which of the following code is wrong inside a UVM driver class?
Hard
Which method in the sequence gets called when user calls sequence.print() method?
Hard
What is UVM RAL (UVM Register Abstraction Layer)?
Hard
What are the different methods for performing Formal Verification?
Hard
Describe Model Checking.
Hard
What are limitations of Formal Verification?
Hard
What are the main components of the power consumption in a CMOS circuit?
Hard
What is Static Power and what all parameters does Static Power consumption depend upon?
Hard
Explain the concept of Multi-Voltage domains and why is it needed?
Hard
What is the need of having level shifters in a design?
Hard
Define the concept of Isolation with respect to Power Domains.
Hard
How does a basic synchronizer circuit look like? Draw a sample
Hard
What is Power Gating and why is it used?
Hard
Draw a block diagram depicting the use of PLL as a frequency synthesizer?
Hard
What are the two different types of constructs used for functional coverage implementation in SystemVerilog?
Hard
What are coverpoints and bins?
Hard
What is the difference between ignore bins and illegal bins?
Hard
What does following bin try to cover?
Hard
What is cross coverage? When is cross coverage useful in Verification?
Hard
How many bins are created by following cross coverage?
Hard
How can we pass arguments to a covergroup and when will that be useful?
Hard
What are the differences between Immediate and Concurrent assertions?
Hard
Explain when the following sequence matches?
Hard
Whats the difference between assert and assume directives in SystemVerilog?
Hard
How to check out a file from CVS Database?
Hard
What is tagging and how to tag a file?
Hard
How to find difference between files from two different versions?
Hard
How can you see the check-in log messages for a file?
Hard
How do you rename a file in GIT?
Hard
What does the result codes G and R in SVN indicates?
Hard
Two bulbs of 10W and 100W are connected in series with an AC power supply of 100V. Which bulb will glow brighter and why?
Hard
There is a triangle and on it are 3 ants, one on each corner, and they are free to move along the sides of the triangle. What is probability that the ants will collide?
Hard
Why does an AHB ERROR response take two cycles?
Hard
What APB assertions are commonly written?
Hard
How would you debug an APB read data mismatch?
Hard
When can BVALID be asserted?
Hard
When can RVALID be asserted?
Hard
Does AXI support early burst termination?
Hard
What AXI assertions are commonly written?
Hard
How will be your approach if functional coverage is 100% but code coverage is too low?
Hard
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