Texas Instruments

I2C uses two wires (SCL, SDA), is multi-master/multi-slave with in-band 7/10-bit addressing and ACKs, but is slower (100k–3.4M) and open-drain. SPI uses four-plus wires (SCLK, MOSI, MISO, and a per-slave chip-select), is full-duplex and much faster, but has no built-in addressing (uses CS lines) and no acknowledgment.

A false path is a topological path that never propagates a real transition of interest (e.g., a path between two asynchronous clock domains, or a test-only path) — it's excluded from timing. A multicycle path is real but is allowed more than one clock cycle to propagate (e.g., a slow datapath whose result is captured every 2 cycles), so setup is relaxed to N cycles.

Phase margin is 180° minus the loop's phase at the unity-gain frequency; it quantifies stability. Around 60° gives a good compromise: minimal peaking/overshoot and a fast, well-damped step response. Too little margin causes ringing or oscillation; too much makes the loop sluggish.