Physical Design + STA8 min readUpdated Aug 8, 2026

Setup and Hold Time in STA, Explained

A clear, diagram-first explanation of setup and hold checks in static timing analysis — the equations, why setup is a frequency problem and hold is a real bug, and how each is fixed.

Setup and hold are the two timing checks every synchronous path must pass. They come up in almost every Physical Design, STA and RTL interview, and candidates who can reason about them from first principles stand out. Here is the whole picture in one page.

The core idea

Data launched by one flip-flop must travel through combinational logic and be captured by the next flip-flop on the same clock — meeting setup before the edge and hold after it.

A flip-flop can only capture data reliably if the data is stable in a window around the active clock edge. It must be stable for a time before the edge (setup) and remain stable for a time after the edge (hold). Violate either and the flop can go metastable or capture the wrong value.

Setup time and the setup check

The setup check says the slowest (max-delay) path from launch to capture must arrive with time to spare before the next clock edge. Rearranged, it sets the fastest clock the design can run at.

Setup requirement (single clock, simplified)

T_clk  >=  T_cq  +  T_comb(max)  +  T_setup  -  T_skew

T_cq       = clk-to-Q of the launch flop
T_comb(max)= longest combinational delay
T_setup    = setup time of the capture flop
T_skew     = capture_clk_arrival - launch_clk_arrival

A setup violation means the path is too slow for the target period. Fixes: pipeline or restructure the logic, upsize/VT-swap cells on the critical path, improve placement, or — worst case — lower the clock frequency.

Hold time and the hold check

The hold check uses the fastest (min-delay) path. New data launched by the same edge must not race through and corrupt the capture flop before it has safely latched the old data.

Hold requirement (single clock, simplified)

T_cq  +  T_comb(min)  >=  T_hold  +  T_skew

T_comb(min)= shortest combinational delay
T_hold     = hold time of the capture flop

Notice the clock period does not appear. That is the crucial insight: hold is independent of frequency. Fixes: insert buffers/delay on the short path or fix clock skew — you cannot slow the clock to escape a hold problem.

Key idea. Setup is a frequency problem — a too-slow path that a slower clock will fix. Hold is a real bug — a too-fast path that fails at any frequency, so it must be fixed in silicon-facing delay.

	Setup	Hold
Path used	Max delay (slowest)	Min delay (fastest)
Depends on T_clk?	Yes	No
Typical fix	Speed up logic / slow clock	Add delay / fix skew
If unfixed	Limits max frequency	Chip fails at any speed

Setup vs hold at a glance.

Common interview questions

Write the setup and hold inequalities and explain each term.
Why can lowering the clock frequency fix setup but never hold?
How does clock skew help one check and hurt the other?
What is negative slack, and how do you read a timing report?
Give three ways to fix a setup violation and two ways to fix a hold violation.

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