Interview Questions
Physical Design + STA
Floorplan to signoff, timing closure & constraints
Interview process
PD/STA loops open with a resume-led hiring-manager round, then technical rounds that weight the implementation flow (floorplan → signoff) and static timing (SDC, exceptions, OCV). Implementation and STA carry the most weight (~60% combined), with power and congestion-versus-timing trade-offs throughout.
Question bank by sub-domain
Pick a sub-domain to study leveled questions, each tagged with the companies that ask it.
Floorplanning
Partitioning, macro placement, power planning
Placement
Congestion, utilization, legalization
Clock Tree Synthesis
Skew, latency, useful skew, clock gating
Routing
Layers, DRC, antenna, shielding
STA
Setup/hold, SDC, clock definitions, paths
Timing Closure
Slack, ECOs, uncertainty, OCV
Low Power (UPF)
Power domains, isolation, retention, MMMC
Signoff
IR drop, EM, DRC/LVS, ESD
Crosstalk / SI
Coupling, noise, delta delay
Tcl / Flow
Scripting the implementation flow
Go deeper
Study the concepts behind these questions, then follow a week-by-week plan.
Physical Design + STA interview roadmap
6 weeks · 24 checkable tasks
Follow the planGuide · 8 minSetup and Hold Time in STA, Explained
A clear, diagram-first explanation of setup and hold checks in static timing analysis — the equations, why setup is a frequency problem and hold is a real bug, and how each is fixed.