Digital Electronics & Verilog

Requirements

• Parameter WIDTH controls the operand size
• sub=1 performs A-B via two's-complement of B
• Overflow is detected from the sign bits, not carry-out
• zero, negative, carry, overflow flags are all correct

You'll be able to

• Explain the difference between carry-out and signed overflow
• Implement subtraction with a single adder and an XOR row

Requirements

• A K-map worked out in comments with the chosen prime implicants
• One structural module using primitive gates
• One behavioral module using a single assign
• A short testbench proving both agree for all 16 inputs

You'll be able to

• Reduce logic with a K-map including don't-cares
• Relate a Boolean expression to both structural and behavioral RTL

Requirements

• A reusable full_adder module (sum, cout)
• A parameterized top that chains carries with a generate-for
• Correct port connections between stages
• A directed testbench covering a few key vectors

You'll be able to

• Build hierarchy by instantiating a leaf cell
• Use generate loops to parameterize structure

Requirements

• N:1 mux selected by $clog2(N) select bits
• Decoder respects the enable input
• Priority encoder resolves the highest set bit and flags valid
• No inferred latches (every output assigned on all paths)

You'll be able to

• Write scalable combinational blocks with parameters
• Distinguish an encoder from a priority encoder

Requirements

• At least 8 operations selected by an opcode
• Arithmetic ops set carry/overflow correctly; logic ops clear them sensibly
• A single combinational result with no latches
• A testbench exercising each opcode and its flags

You'll be able to

• Fold an arithmetic and logic datapath into one block
• Reason about which flags are meaningful per operation

Requirements

• Combinational logic uses blocking (=) in always @*
• Sequential logic uses nonblocking (<=) in always @(posedge clk)
• Every combinational output is assigned on all paths (no latch)
• A note explaining the simulation-vs-synthesis reason for each rule

You'll be able to

• Apply the blocking/nonblocking rule correctly
• Recognize and remove an inferred latch

Requirements

• Counter supports up/down, load, enable and synchronous reset
• Shift register supports the four standard modes via a 2-bit control
• Consistent reset polarity and style across both
• A testbench that checks wrap-around and each shift mode

You'll be able to

• Code clocked registers with control inputs cleanly
• Choose and justify synchronous vs asynchronous reset

Requirements

• Overlapping matches are detected (e.g. 1011011)
• A clean three-block or two-block FSM coding style
• Both Mealy and Moore versions with named states
• A testbench and a note on the one-cycle timing difference

You'll be able to

• Draw and code a state diagram for a pattern detector
• Explain when Mealy vs Moore output timing matters

Requirements

• A pure function (no side effects) for parity
• A clog2 function used to size a bus at elaboration
• The automatic keyword where recursion or reentrancy is needed
• A short check that parity toggles as expected

You'll be able to

• Factor repeated logic into functions
• Size buses from parameters with clog2

Requirements

• Parameterized DEPTH and WIDTH using clog2 addressing
• Synchronous write; choose and document read-first or write-first
• Register file: two combinational (or registered) reads, one write
• A testbench that hits the read-during-write corner

You'll be able to

• Model memories the way synthesis tools infer them
• Reason about read/write collision behavior

Requirements

• Parameterized DEPTH (power of two) and WIDTH
• full and empty derived from wptr/rptr with the extra MSB trick
• No overflow on write-when-full or underflow on read-when-empty
• A testbench that fills, drains and interleaves operations

You'll be able to

• Implement pointer-based FIFO flag logic
• Explain the extra-bit trick for full vs empty

Requirements

• No inferred latches (full assignment or defaults)
• One consistent reset scheme with constant reset values
• Only synthesizable constructs (no delays, static loop bounds)
• A short before/after note on each issue

You'll be able to

• Separate simulation-only code from synthesizable RTL
• Apply a consistent, tool-friendly reset style

Requirements

• Stimulus generation (directed plus a few randomized vectors)
• A behavioral golden model computing the expected output
• Automatic comparison with an error count, not manual waveform reading
• A final PASS/FAIL banner with the mismatch count

You'll be able to

• Write a testbench that checks itself instead of eyeballing waves
• Separate stimulus, reference model and checker