DV Capstone Projects
Put the whole toolkit together on real verification projects: a synchronous FIFO testbench, a UVM environment for an APB register block with RAL, an AXI-Lite slave environment, an async-FIFO CDC project, and a small SoC-lite capstone — each with stimulus, checking, coverage and a regression you can show an interviewer.
By the end you can
- Verify real DUTs end to end with reusable environments
- Combine constrained-random stimulus, scoreboards and coverage
- Apply UVM, RAL and protocol knowledge on integrated problems
- Produce portfolio projects you can defend line by line
0 / 5 assignments done
Move each assignment through the stages — progress saves automatically.
Project 1 — Synchronous FIFO verification
0/1A complete SystemVerilog testbench for a FIFO: constrained-random traffic, a reference model, full/empty checks and coverage.
Verify a synchronous FIFO end to end
Take a synchronous FIFO DUT and build a full class-based testbench: a generator of constrained-random read/write traffic (including full and empty pressure), a reference-model scoreboard that predicts data order, flag checks, and functional coverage of depth occupancy and corner conditions.
Requirements
- Constrained-random stimulus that reaches full and empty
- A queue-based reference model checking data order
- Assertions for full/empty correctness (no overflow/underflow)
- Coverage of occupancy levels and simultaneous read/write
You'll be able to
- Assemble a complete SV testbench from parts you built earlier
- Verify ordering, flags and corners together
Submitting your solution link marks this assignment done.
A full worked solution with a step-by-step walkthrough — included with the domain pack and All-Access. Try it yourself first.
Project 2 — APB register block with UVM + RAL
0/1A UVM environment for a memory-mapped APB register block, driven and checked through the register abstraction layer.
UVM + RAL environment for an APB register block
Build a UVM environment for an APB slave with several registers (RW, RO, W1C). Model the registers with RAL, drive them through an APB agent and adapter, add a predictor, and write tests that check reset values, read/write access policies, and W1C behavior.
Requirements
- An APB UVM agent (driver, monitor, sequencer)
- A RAL model with an adapter and predictor
- Built-in-style tests: reset value, read/write, and access-policy
- Coverage of register accesses and the W1C path
You'll be able to
- Integrate a UVM agent with a RAL model
- Verify register access policies systematically
Submitting your solution link marks this assignment done.
A full worked solution with a step-by-step walkthrough — included with the domain pack and All-Access. Try it yourself first.
Project 3 — AXI-Lite slave environment
0/1A UVM environment for an AXI-Lite slave: channel handshakes, a memory-model scoreboard, and protocol coverage.
Verify an AXI-Lite slave in UVM
Build a UVM environment for an AXI-Lite slave (memory-mapped). Drive AW/W/B and AR/R with correct VALID/READY handshakes, model the slave memory in a scoreboard, add SVA channel checks, and cover read/write across all address regions.
Requirements
- An AXI-Lite agent handling all five channels
- A memory-model scoreboard for write-then-read
- SVA for the VALID/READY handshake per channel
- Coverage of direction × region and back-pressure
You'll be able to
- Verify an AXI-Lite slave end to end
- Combine protocol assertions with a data scoreboard
Submitting your solution link marks this assignment done.
A full worked solution with a step-by-step walkthrough — included with the domain pack and All-Access. Try it yourself first.
Projects 4 & 5 — CDC block and a SoC-lite capstone
0/2A CDC-focused project (async FIFO) and a small multi-block capstone that ties protocol, CDC and UVM together.
Project 4 — Async FIFO / CDC verification
Verify a dual-clock async FIFO: drive independent read/write clocks with a range of frequency ratios, check data integrity and ordering across the crossing, assert Gray-pointer one-bit-change, and confirm no data loss under full/empty pressure.
Requirements
- Independent, configurable read/write clocks
- Data-integrity + ordering check across the CDC
- Assertions for Gray-code one-bit change and flag safety
- Stress at several clock ratios including near-equal
You'll be able to
- Verify a real CDC block dynamically
- Combine CDC assertions with data checking
Submitting your solution link marks this assignment done.
A full worked solution with a step-by-step walkthrough — included with the domain pack and All-Access. Try it yourself first.
Project 5 — SoC-lite capstone
Verify a small SoC-lite: an APB (or AXI-Lite) interconnect fronting two slaves (e.g. a register block and a memory), with a UVM environment, a virtual sequence coordinating traffic, a scoreboard per slave, and a regression across seeds with merged coverage.
Requirements
- A UVM env with a bus agent and two slave models
- A virtual sequence generating mixed traffic to both slaves
- Per-slave scoreboards and protocol assertions
- A multi-seed regression with merged coverage and a sign-off summary
You'll be able to
- Verify an integrated multi-block system
- Run a regression and argue coverage closure
Submitting your solution link marks this assignment done.
A full worked solution with a step-by-step walkthrough — included with the domain pack and All-Access. Try it yourself first.
Put it to work
Drill the matching interview questions, then see where this module sits in the full Design Verification roadmap.