Communication Protocols — APB / AHB / AXI
Master the AMBA protocols DV interviews live on: the simple APB, the pipelined AHB, and the fully concurrent AXI with its five channels, bursts, IDs and out-of-order responses — then verify a slave with SVA protocol checks, a scoreboard and functional coverage.
By the end you can
- Explain and drive APB, AHB and AXI transfers
- Reason about handshakes, bursts, IDs and outstanding transactions
- Write SVA protocol checks for bus handshakes
- Verify a bus slave with a scoreboard and coverage
0 / 9 assignments done
Move each assignment through the stages — progress saves automatically.
APB — the simple starting point
0/2The two-phase APB handshake with wait states and errors — and a first bus verification component.
APB read/write with wait states and error
Model an APB slave register block: decode PSEL/PENABLE for the setup and access phases, support PREADY wait states, and return PSLVERR on an illegal access. Drive it with a small master task.
Requirements
- Correct SETUP (PSEL=1, PENABLE=0) then ACCESS (PENABLE=1) phases
- PREADY-based wait states honored by the master
- PSLVERR asserted for an out-of-range or read-only write
- Read returns the last written value
You'll be able to
- Explain the APB two-phase handshake
- Handle wait states and error responses
Submitting your solution link marks this assignment done.
A full worked solution with a step-by-step walkthrough — included with the domain pack and All-Access. Try it yourself first.
Verify an APB slave
Build a tiny verification component for the APB slave: a driver that issues reads/writes, a monitor that reconstructs transfers, and checks that every access follows the setup→access phase rules and that read-back matches writes.
Requirements
- A driver task for read and write transfers
- A monitor reconstructing (addr, data, write, err) transactions
- A phase-legality check (no PENABLE without PSEL setup)
- A read-after-write data check
You'll be able to
- Stand up a minimal bus VIP
- Check protocol legality while checking data
Submitting your solution link marks this assignment done.
A full worked solution with a step-by-step walkthrough — included with the domain pack and All-Access. Try it yourself first.
AHB — the pipelined bus
0/2AHB's address/data pipelining, bursts, and the wait/split/retry responses that trip people up.
AHB single and burst transfers
Model AHB address/data pipelining: the address phase of transfer N overlaps the data phase of N-1. Drive single transfers and an incrementing burst (HBURST), honoring HREADY.
Requirements
- Overlapped address/data phases (pipelined)
- HTRANS (IDLE/BUSY/NONSEQ/SEQ) used correctly
- An INCR burst with correct address sequencing
- HREADY back-pressure respected
You'll be able to
- Explain AHB address/data pipelining
- Drive bursts with correct HTRANS/HADDR
Submitting your solution link marks this assignment done.
A full worked solution with a step-by-step walkthrough — included with the domain pack and All-Access. Try it yourself first.
AHB wait, split and retry responses
Extend the AHB slave to drive the two-cycle HRESP responses (ERROR and, conceptually, RETRY/SPLIT): show how HREADY/HRESP combine and how the master must react (e.g. cancel the pipelined address).
Requirements
- Two-cycle ERROR response (HREADY low then high with HRESP=ERROR)
- Correct master reaction to an ERROR mid-burst
- A note on RETRY/SPLIT semantics and re-arbitration
- Assertions that HRESP is only ERROR with the right HREADY pattern
You'll be able to
- Handle AHB two-cycle responses
- Explain the master's reaction to error/retry/split
Submitting your solution link marks this assignment done.
A full worked solution with a step-by-step walkthrough — included with the domain pack and All-Access. Try it yourself first.
AXI — channels, bursts & ordering
0/3The five independent channels, VALID/READY handshake, bursts, IDs, outstanding transactions and out-of-order responses.
AXI five channels and a write transaction
Explain and drive a full AXI write: address on AW, data (with WLAST and WSTRB) on W, and a response on B, each with its own VALID/READY handshake. Show the handshake rule that neither side may wait on the other's assertion.
Requirements
- AW, W, B channels each with independent VALID/READY
- WLAST on the final data beat and WSTRB byte enables
- A B-channel response consumed after the burst
- The VALID-before-READY independence rule respected
You'll be able to
- Name the five AXI channels and their roles
- Drive a correct AXI write burst
Submitting your solution link marks this assignment done.
A full worked solution with a step-by-step walkthrough — included with the domain pack and All-Access. Try it yourself first.
AXI bursts, IDs and outstanding transactions
Drive INCR and WRAP bursts with correct address generation, use AXID to launch multiple outstanding transactions, and track how many are in flight. Explain the WRAP boundary rule.
Requirements
- INCR and WRAP address generation (WRAP wraps at the boundary)
- Multiple outstanding transactions via IDs
- A counter of in-flight transactions per ID
- AWSIZE/AWLEN used to compute addresses
You'll be able to
- Generate AXI burst addresses correctly
- Reason about outstanding transactions and IDs
Submitting your solution link marks this assignment done.
A full worked solution with a step-by-step walkthrough — included with the domain pack and All-Access. Try it yourself first.
AXI out-of-order responses and ID matching
Handle AXI's ordering model: responses for different IDs may return out of order, but same-ID transactions stay ordered. Build a checker that matches responses to requests by ID and flags any same-ID reordering.
Requirements
- Requests tracked per ID in order
- Responses matched by ID to the oldest outstanding of that ID
- Detection of same-ID out-of-order (a violation)
- Cross-ID reordering accepted as legal
You'll be able to
- Explain the AXI ordering model
- Check ID-based response matching
Submitting your solution link marks this assignment done.
A full worked solution with a step-by-step walkthrough — included with the domain pack and All-Access. Try it yourself first.
Protocol verification
0/2Turn protocol knowledge into checks: SVA for the handshakes, plus a scoreboard and coverage for a small bus VIP.
SVA protocol checker for handshakes
Write concurrent assertions for a VALID/READY handshake: once VALID is asserted it must stay high until READY (stability), payload must be stable while VALID waits, and no READY-without-VALID data capture. Reuse for AXI-style channels.
Requirements
- VALID held until the handshake completes
- Payload stability while VALID && !READY
- No data captured without a completed handshake
- Assertions parameterized to reuse across channels
You'll be able to
- Encode handshake rules as SVA
- Reuse protocol checks across channels
Submitting your solution link marks this assignment done.
A full worked solution with a step-by-step walkthrough — included with the domain pack and All-Access. Try it yourself first.
Scoreboard and coverage for a bus VIP
For one protocol (say APB or AXI-Lite), build a scoreboard that models the slave memory and checks read-back, plus a covergroup for address regions, transfer types, burst lengths and error responses.
Requirements
- A memory-model scoreboard checking write-then-read
- Coverpoints for region, direction, size/len and error
- A cross of direction × region
- A report tying coverage to the protocol features
You'll be able to
- Check a bus slave end to end
- Measure protocol feature coverage
Submitting your solution link marks this assignment done.
A full worked solution with a step-by-step walkthrough — included with the domain pack and All-Access. Try it yourself first.
Put it to work
Drill the matching interview questions, then see where this module sits in the full Design Verification roadmap.