VLSI Mentoring

Design for Test · Interview Questions

Interview process

DFT loops open with a resume-led hiring-manager round, then technical rounds that weight testability architecture (scan, MBIST, JTAG) and ATPG/coverage, plus how you trade test cost against coverage. Architecture and coverage carry the most weight (~60% combined).

Back to Design for Test

The rounds, in order

5 rounds
  1. 1

    Hiring manager round

    45–60 min · hiring manager

    Resume-led screen that also samples DFT and behavioral signal

    What they ask
    • Walk through your resume, then a DFT task you owned (~70–80%)
    • Your specific role and responsibilities versus the team's
    • A quick scan or ATPG question (~10%)
    • One or two behavioral prompts — ownership, deadlines (~10%)
  2. 2

    DFT architecture round

    45–60 min · onsite panel≈30% weight

    Testability infrastructure

    What they ask
    • Scan insertion and controllability/observability
    • MBIST and memory repair
    • JTAG / boundary scan (IEEE 1149.1)
    • IEEE 1500 / 1687 for core and instrument access
  3. 3

    ATPG & coverage round

    45–60 min · onsite panel≈30% weight

    Patterns, faults, and cost

    What they ask
    • Fault models: stuck-at, transition, bridging
    • Raise fault coverage on a stubborn block
    • Compression ratio versus diagnosis
    • At-speed and low-power test
  4. 4

    Resume-based round

    45–60 min · onsite panel≈20% weight

    Deep dive on your DFT work

    What they ask
    • End-to-end DFT flow you owned
    • A test-cost versus coverage decision you made
    • Pattern debug and silicon bring-up
    • Scripting and flow automation you built
  5. 5

    Behavioral round

    45 min · hiring manager / peer panel≈20% weight

    Cross-team collaboration

    What they ask
    • A test-cost decision you drove
    • Working with PD and DV
    • A schedule you protected
    • Thoughtful questions for the team

How to prepare

  • Resume stories: rehearse a DFT task end to end and lead with your own role, not the team's.
  • Architecture: explain scan, MBIST + repair, and JTAG/boundary scan for a block.
  • Coverage: know fault models and how controllability/observability drive coverage.
  • Trade-offs: be ready on compression ratio versus diagnosis and test cost versus coverage.
  • Debug: prepare a pattern-debug or bring-up story with a crisp root cause.

Practice these sub-domains

Drill leveled questions for each area of the Design for Test loop.

DFTScan Design1DFTATPG0DFTMBIST0DFTJTAG / Boundary Scan0DFTTest Compression1DFTFault Models2DFTDFT Architecture1DFTLow-Power DFT0DFTDiagnosis0