Interview process

1. 1

   Hiring manager round

   45–60 min · hiring manager

   Resume-led screen that also samples coding and behavioral signal

   What they ask

   • Walk through your resume, then a bring-up or driver you owned (~70–80%)
   • Your specific role and responsibilities versus the team's
   • A short C coding question (~10%)
   • One or two behavioral prompts — ownership, deadlines (~10%)
2. 2

   Coding round

   45–60 min · video + coding pad≈30% weight

   Low-level C and fundamentals

   What they ask

   • Pointers, volatile, and bit manipulation
   • What is legal inside an ISR
   • A small C problem on a shared pad
   • Data structures for constrained memory
3. 3

   Systems & FPGA round

   45–60 min · onsite + board≈30% weight

   Drivers, RTOS, and hardware

   What they ask

   • Design a peripheral driver and its DMA/interrupt flow
   • RTOS: scheduling, priority inversion, mutex vs semaphore
   • FPGA timing and resource trade-offs
   • I2C/SPI/UART framing and bring-up
4. 4

   Resume-based round

   45–60 min · onsite panel≈20% weight

   Deep dive on a bring-up you led

   What they ask

   • End-to-end walkthrough of a project you owned
   • HW/SW co-debug with JTAG, gdb, or a logic analyzer
   • A firmware bug you root-caused
   • Trade-offs and decisions you made
5. 5

   Behavioral round

   45 min · hiring manager / peer panel≈20% weight

   End-to-end ownership and collaboration

   What they ask

   • A bring-up you led end to end
   • HW/SW collaboration across teams
   • A deadline you protected
   • Thoughtful questions for the team

How to prepare

• Resume stories: rehearse a bring-up end to end and lead with your own role, not the team's.
• Coding: sharpen pointers, volatile, bit manipulation, and what is legal in an ISR.
• Systems: design a clean peripheral driver and reason about DMA/interrupt flow.
• RTOS: know scheduling, priority inversion, and mutex versus semaphore.
• Debug: prepare a hardware bring-up story using JTAG, gdb, or a logic analyzer.

Practice these sub-domains

Drill leveled questions for each area of the Embedded / Firmware / FPGA loop.