Interview process

1. 1

   Hiring manager round

   45–60 min · hiring manager

   Resume-led screen that also samples coding and behavioral signal

   What they ask

   • Walk through your resume, then go deep on one block you designed (~70–80%)
   • Your specific role and responsibilities versus the team's
   • A short Verilog/SystemVerilog coding question (~10%)
   • One or two behavioral prompts — ownership, deadlines (~10%)
2. 2

   Coding round

   45–60 min · video + coding pad≈30% weight

   Clean, synthesizable Verilog/SystemVerilog

   What they ask

   • Blocking vs non-blocking and glitch-free logic
   • Code an FSM, FIFO, or arbiter live
   • Parameterized, reusable RTL
   • A small logic or algorithmic problem
3. 3

   Micro-architecture round

   45–60 min · onsite panel≈30% weight

   Spec-to-micro-architecture and trade-offs

   What they ask

   • Turn a one-line spec into a block diagram and FSM
   • Pipeline for throughput versus latency
   • Datapath, arbiter, or interconnect design
   • Area, power, and timing trade-offs
4. 4

   CDC & timing round

   45–60 min · onsite panel≈20% weight

   Robust clocking and timing closure

   What they ask

   • Multi-bit CDC: handshakes and async FIFOs
   • Reset synchronization and metastability
   • Fix a critical timing path (retiming, pipelining)
   • Lint and CDC signoff
5. 5

   Behavioral round

   45 min · hiring manager / peer panel≈20% weight

   Ownership and cross-team collaboration

   What they ask

   • A hard design decision you owned
   • A cross-team dependency you managed
   • A design bug you caught before silicon
   • Thoughtful questions for the team

How to prepare

• Resume stories: rehearse each block end to end and lead with your own role, not the team's.
• Coding: practice turning a one-line spec into a clean FSM, FIFO, or arbiter in synthesizable RTL under time pressure.
• Micro-architecture: be ready to trade pipelining, throughput, and area/power/timing out loud.
• CDC: be fluent on two-flop synchronizers, handshakes, async FIFOs, and when each is safe.
• Timing: expect a live path fix — know retiming, pipelining, and logic-restructuring trade-offs.

Practice these sub-domains

Drill leveled questions for each area of the RTL / Micro-architecture Design loop.