Interview Questions
RTL / Micro-architecture Design
Synthesizable Verilog/SV, pipelining & CDC
Interview process
RTL loops open with a resume-led hiring-manager round, then technical rounds that weight live synthesizable coding, micro-architecture reasoning, and robust clocking. Coding and micro-architecture carry the most weight (~60% combined), with CDC and timing the classic make-or-break topics.
Question bank by sub-domain
Pick a sub-domain to study leveled questions, each tagged with the companies that ask it.
Digital Design
Combinational & sequential building blocks
Verilog / SV RTL
Synthesizable coding style, blocking vs non-blocking
FSM Design
Moore/Mealy, encoding, one-hot, deadlock
Clock Domain Crossing
Synchronizers, MTBF, gray-code FIFOs, RDC
Low-Power RTL
Clock gating, power intent, isolation
Pipelining & Timing
Retiming, hazards, throughput vs latency
Arithmetic / Datapath
Adders, multipliers, saturation, fixed-point
Memories & FIFOs
Sync/async FIFO depth, register files, ECC
Lint / Synthesis-aware
Latches, inferred logic, timing exceptions
Protocols
Valid/ready, AXI-lite, credit schemes
Go deeper
Study the concepts behind these questions, then follow a week-by-week plan.
RTL / micro-architecture interview roadmap
6 weeks · 24 checkable tasks
Follow the planGuide · 8 minClock Domain Crossing (CDC) and Metastability
Why signals crossing clock domains go metastable, how the two-flop synchronizer works, and when you must use gray codes, handshakes or async FIFOs instead — with a diagram and RTL.