Study plans
Build it — don't just read it
Week-by-week hands-on assignments that turn concepts into working RTL and testbenches, tracked from not-started to done. Start with Design Verification.
Design Verification
Digital Electronics & Verilog
Rebuild digital logic in Verilog the way DV interviews expect — number systems and Boolean minimization, combinational and sequential blocks, Mealy/Moore FSMs, memories and FIFOs, and a synthesizable coding style checked by a self-checking testbench.
SystemVerilog Hands-On
Get fluent in the verification language interviewers actually probe: dynamic data structures, OOP for reusable testbench components, constrained randomization, interfaces and clocking blocks, processes and IPC, and finally SystemVerilog assertions and functional coverage.
UVM Hands-On
Build a UVM environment piece by piece the way an interview drills it: driver/monitor/agent and scoreboard, phasing and objections, the factory and config_db, reporting, sequences and virtual sequences, TLM analysis ports, and a register model with an adapter and predictor.
Verification Concepts — End-to-End
The end-to-end functional-verification cycle interviewers expect you to reason about: writing a verification plan, architecting a layered testbench, choosing directed vs constrained-random stimulus, checking with scoreboards and reference models, understanding simulation scheduling and races, and closing coverage through regressions and triage.
Communication Protocols — APB / AHB / AXI
Master the AMBA protocols DV interviews live on: the simple APB, the pipelined AHB, and the fully concurrent AXI with its five channels, bursts, IDs and out-of-order responses — then verify a slave with SVA protocol checks, a scoreboard and functional coverage.
Clock Domain Crossing & Reset
The CDC and reset questions that dominate DV interviews: why metastability happens and how a two-flop synchronizer tames it, pulse and multi-bit crossings with Gray code and handshakes, async FIFOs, reset synchronizers (async assert / sync deassert), reset domain crossing, and how to actually verify all of it.
DV Capstone Projects
Put the whole toolkit together on real verification projects: a synchronous FIFO testbench, a UVM environment for an APB register block with RAL, an AXI-Lite slave environment, an async-FIFO CDC project, and a small SoC-lite capstone — each with stimulus, checking, coverage and a regression you can show an interviewer.
Coming soon
We're building Design Verification first. These tracks get the same hands-on study plans next.